An apparatus (54) is provided for preventing cross conduction in a synchronous rectifier of a DC-DC converter (10). The DC-DC converter has an input MOSFET switch (26) coupled to primary windings (22) of an isolation transformer (20), an output MOSFET switch (30) coupled to secondary windings (24) of the isolation transformer, and a complementary output MOSFET switch (34) coupled to an output terminal (14). A synchronous rectifier timing circuit (54) comprises a first timing output signal circuit (62) responsive to a pulse width modulated signal for providing first and second timing output signals (55, 56) that switches low at time t1 and high at time t4 to control the input MOSFET switch and output MOSFET switch, respectively, and a second timing output signal circuit (64) responsive to the pulse width modulated signal for providing a third timing output signal (58) that switches high at time t2 and low at time t3 to control the complementary output MOSFET switch.

A power source with an arrangement for restricting short-circuit current includes at least a primary-side switch block, a transformer unit and a rectifier. The rectifier includes switching transistors for rectifying the secondary side of the transformer. Operation of the rectifier depends on a control from a pulse-forming part of the primary-side switch block. Control for the switching transistors in the rectifier is interrupted when the output current of the rectifier exceeds a limit value. At least one other switch element is arranged parallel to each of the switching transistors in the rectifier to realize a secondary-side rectification in an overload situation.

An undershoot eliminator circuit is disclosed that avoids the occurrence of a negative undershoot that typically happens when an isolated DC-DC converter with a secondary side synchronous driver that is turned off. The undershoot eliminator circuit functions to discharge an energy storage element in an auxiliary supply on said secondary side of said converter. The circuit includes a clamp transistor having a gate terminal, a source terminal, and a drain terminal, the drain terminal of the transistor connected to said storage element, the source terminal of the transistor connecting to the output of the converter; means for trapping charge on the gate terminal of the clamp transistor while said converter is on; and means for coupling the voltage on the output of the converter to the gate terminal, such that, when said converter goes off and its output voltage begins to drop, the trapped charge causes the gate-to-source voltage of the clamp transistor to increase until the gate of the transistor is sufficiently saturated to cause it to turn on for a sufficient time to discharge the storage element. The undershoot eliminator circuit preferably employs a capacitor for trapping a charge on the gate terminal of the clamp transistor. The storage capacitor is quickly discharged to avoid a negative undershoot from occurring when the DC/DC power converter is turned off.

A power supply converts a first direct-current voltage into a second direct-current voltage and outputs the second direct-current voltage. The power supply includes a reference voltage generating circuit for generating a reference voltage, a control circuit for controlling an output voltage in accordance with the reference voltage, and a short-circuit detecting circuit for performing an output short-circuit protection operation, when short circuiting occurs at the output, by detecting the occurrence of short circuiting and by decreasing the reference voltage so that the output voltage is decreased.

There is disclosed a synchronized rectifier type switching power source device in which losses and noise generation due to differences in operating delay times in the input and output switching elements can be suppressed. A signal timing adjusting device is provided for controlling the timing of the control signal applied to the first switching device provided in the input side and those of the control signals applied to the second and third switching devices provided in the output side, so that the control signal is applied to the first switching device with a timing delayed as compared with the timings of the control signals applied to the second and third switching devices to thereby compensate for the operating time delay among the first switching device and the second and third switching devices due to the differences in the voltage durability and the current capacity among these switching devices.