Semiconductor integrated circuit device and method of activating the same

Claims

We claim:

1. A semiconductor integrated circuit device comprising:

a plurality of circuit blocks divided according to respective functions and respectively set so as to perform circuit operations in response to operation control signals; and

a power switch circuit composed of a plurality of switch MOSFETs, said power switch MOSFETs being provided in parallel between a power line for delivering an operating voltage supplied from an external terminal and internal power lines provided for said respective circuit blocks and being stepwise turned on in response to control signals produced by successively delaying the operation control signals.

2. A semiconductor integrated circuit device comprising:

an input circuit block responsive to an input signal supplied from a first external terminal, said input signal including an operation start signal;

an internal circuit block activated in response to the input signal inputted through said input circuit block;

an output circuit block for transmitting a signal outputted from said internal circuit block to an external terminal; and

internal power switch circuits each composed of a plurality switch MOSFETs provided in parallel between a power line for applying an operating voltage supplied from a second external terminal and a first internal power line for a first circuit portion in said internal circuit block, which is free of need for a storage operation upon reaching a non-operating state, said switch MOSFETs being stepwise turned on in response to controls signals produced by successively delaying a start signal supplied through said input circuit block.

3. A semiconductor integrated circuit device according to claim 2, wherein said input circuit block, a second circuit portion of said internal circuit block, which needs a storage operation, and said output circuit block are respectively regularly supplied with the operating voltage from the power line.

4. A semiconductor integrated circuit device according to claim 3, wherein said internal circuit block is composed of CMOS circuits, said each CMOS circuit having a first circuit portion which includes a circuit whose output signal is low in level when said first circuit portion is placed in a non-operating state, said circuit being electrically connected to the first internal power line providing a source voltage, and a circuit whose output signal is high in level, which is electrically connected to the second internal power line associated with a ground potential, and said internal power switch circuits each composed of a plurality of switch MOSFETs stepwise turned on in response to the control signals formed by delaying the start signal in turn, are respectively provided between the first internal power line and the power line and between the second internal power line and a ground line.

5. A semiconductor integrated circuit device according to claim 4, wherein each of P channel MOSFETs and N channel MOSFETs, which constitute said each CMOS circuit, has a low threshold voltage.

6. A semiconductor integrated circuit device according to claim 5,

said input circuit block and said output circuit block are respectively composed of CMOS circuits, and threshold voltages of the P channel MOSFETs and N channel MOSFETs constituting said each CMOS circuit and threshold voltages of MOSFETs constituting said each internal power switch circuit are set so as to be higher than those of the P channel MOSFETs and N channel MOSFETs of said each CMOS circuit of said internal circuit block.

7. A semiconductor integrated circuit device according to claim 6, wherein said threshold voltages are respectively set using a MOSFET dependence on a channel length, and counter-doped layers, each of which is of the conductive type similar to the source and drain of each MOSFET and contains a low concentration of impurities, are respectively formed on the surfaces of channel regions.

8. A semiconductor integrated circuit device according to claims 3 or 4, wherein said internal circuit block is divided into a plurality of blocks according to its operation sequence and said start signal is delayed in synchronism with the operation sequence so as to be supplied to said internal power switch circuit.

9. A semiconductor integrated circuit device according to claim 2, wherein said input circuit block is supplied with an address signal and a control signal in an address multiplex system,

said internal circuit block comprises a memory array using dynamic memory cells, an X-system address select circuit thereof, and a Y-system address select circuit, and

said output circuit block is used as a data input/output circuit.

10. A semiconductor integrated circuit device according to claim 9, wherein each internal power switch circuit provided in the Y-system address select circuit is composed of one or a plurality of MOSFETs set so as to provide the flow of an operating current necessary for the operation of said internal power switch circuit, and a control signal supplied to the gate of said each MOSFET is set so that its change becomes gentle.

11. A semiconductor integrated circuit device according to claim 4, wherein a short-circuit switch MOSFET, temporarily turned on when said internal power switch MOSFETs associated with said each first internal power line and said each second internal power line are turned off, is provided between said first internal power line and said second internal power line.

12. A semiconductor integrated circuit device comprising:

a first voltage line supplied with a first voltage;

a second voltage line supplied with a second voltage higher than the first voltage;

a third voltage line;

at least one internal circuit connected to said first voltage line and said third voltage line and activated in response to a voltage on said first voltage line and a voltage on said third voltage line;

first MOSFETs having source-to-drain paths respectively connected between said second voltage line and said third voltage line;

second MOSFETs having source-to-drain paths respectively connected between said second voltage line and said third voltage line; and

a control circuit for controlling said first and second MOSFETs so that said first and second MOSFETs are respectively changed from an off state to an on state with different timings.

13. A semiconductor integrated circuit device according to claim 12, wherein said first and second MOSFETs are P channel type MOSFETs.

14. A semiconductor integrated circuit device according to claim 12, wherein said control circuit further includes a delay circuit.

15. A semiconductor integrated circuit device according to claim 12, further comprising a memory array having a plurality of memory cells and wherein said internal circuit includes an address decoder provided so as to correspond to said memory array.

16. A semiconductor integrated circuit device according to claim 12, wherein said first voltage is a ground voltage, said second voltage is a source voltage, said first voltage line is a ground voltage line, said second voltage line is a source voltage line, and said third voltage line is a line corresponding to the source voltage.

17. A semiconductor integrated circuit device comprising:

a first main voltage line supplied with a first voltage;

a second main voltage line supplied with a second voltage higher than the first voltage;

a first sub voltage line supplied with a voltage corresponding to the first voltage;

at least one internal circuit connected to said first sub voltage line and said second main voltage line and activated based on the first voltage and the second voltage;

first MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said first sub voltage line;

second MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said first sub voltage line; and

a first control circuit for controlling said first and second MOSFETs so that said first and second MOSFETs are respectively changed from an off state to an on state with different timings.

18. A semiconductor integrated circuit device according to claim 17, further comprising:

a second sub voltage line supplied with a voltage corresponding to the second voltage;

third MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said second sub voltage line;

fourth MOSFETs having source-to-drain paths respectively connected between said main voltage line and said second sub voltage line; and

a second control circuit for controlling said third and fourth MOSFETs so that said third and fourth MOSFETs are respectively changed from an off state to an on state with different timings.

19. A semiconductor integrated circuit device according to claim 18, wherein said first voltage is a ground voltage, said second voltage is a source voltage, said first main voltage line is a ground voltage line, said second main voltage line is a source voltage line, said first sub voltage line is a line corresponding to the ground voltage and said second sub voltage line is a line corresponding to the source voltage.

20. A semiconductor integrated circuit device comprising:

a first main voltage line supplied with a first voltage;

a second main voltage line supplied with a second voltage higher than the first voltage;

a first sub voltage line supplied with a voltage corresponding to the second voltage;

a first internal circuit connected to said first sub voltage line and said first main voltage line and activated based on the first voltage and the second voltage;

a second internal circuit directly connected to said first main voltage line and said second main voltage line and activated based on the first voltage and the second voltage;

first MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said first sub voltage line;

second MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said first sub voltage line; and

a first control circuit for controlling said first and second MOSFETs so that said first and second MOSFETs are respectively changed from an off state to an on state with different timings.

21. A semiconductor integrated circuit device according to claim 20, further comprising:

a memory array having a plurality of memory cells, and

wherein said first internal circuit includes an address decoder provided so as to correspond to said memory array, and

said second internal circuit includes an address input buffer.

22. A semiconductor integrated circuit device according to claim 20, wherein said first voltage is a ground voltage, said second voltage is a source voltage, said first main voltage line is a ground voltage line, said second main voltage line is a source voltage line and said first sub voltage line is a line corresponding to the source voltage.

23. A semiconductor integrated circuit device comprising:

a first main voltage line supplied with a first voltage;

a second main voltage line supplied with a second voltage different from the first voltage;

a first sub voltage line supplied with a voltage corresponding to the first voltage;

a second sub voltage line supplied with a voltage corresponding to the first voltage;

a first circuit connected to said first sub voltage line and activated based on the first and second voltages;

a second circuit connected to said second sub voltage line and activated based on the first and second voltages;

first MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said first sub voltage line;

second MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said first sub voltage line;

third MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said second sub voltage line;

fourth MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said second sub voltage line;

a first control circuit for controlling said first and second MOSFETs so that each second MOSFET is changed from an off state to an on state after each first MOSFET has been changed from an off state to an on state; and

a second control circuit for controlling said third and fourth MOSFETs so that each third MOSFET is changed from an off state to an on state after each first MOSFET has been changed from the off state to the on state, and each fourth MOSFET is changed from an off state to an off state after each third MOSFET has been changed from the off state to the on state.

24. A semiconductor integrated circuit device according to claim 23, further comprising:

a third sub voltage line supplied with a voltage corresponding to the second voltage and connected to said first circuit;

a fourth sub voltage line supplied with a voltage corresponding to the second voltage and connected to said second circuit;

fifth MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said third sub voltage line;

sixth MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said third sub voltage line;

seventh MOSFETs having source-to-drain paths respectively connected between said main voltage line and said fourth sub voltage line;

eighth MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said fourth sub voltage line;

a third control circuit for controlling said fifth and sixth MOSFETs so that each sixth MOSFET is changed from an off state to an on state after each fifth MOSFET has been changed from an off state to an on state; and

a fourth control circuit for controlling said seventh and eighth MOSFETs so that each seventh MOSFET is changed from an off state to an on state after each fifth MOSFET has been changed from the off state to the on state, and each eighth MOSFET is changed from an off state to an off state after each seventh MOSFET has been changed from the off state to the on state.

25. A semiconductor integrated circuit device according to claim 24, wherein said first voltage is a ground voltage, said second voltage is a source voltage, said first main voltage line is a ground voltage line, said second main voltage line is a source voltage line, said first sub voltage line is a voltage line corresponding to the first voltage, said second sub voltage line is a voltage line corresponding to the first voltage, said third sub voltage line is a voltage line corresponding to the second voltage, and said fourth sub voltage line is a voltage line corresponding to the second voltage.

26. A method of activating a semiconductor integrated circuit device having a first voltage line supplied with a first voltage, a second voltage line supplied with a second voltage higher than the first voltage, a circuit activated in response to the first and second voltages, a first switch MOSFET disposed between said first voltage line and said circuit, and a second switch MOSFET disposed between said second voltage line and said circuit, said method comprising:

a first step of transferring the first voltage on said first voltage line to said circuit through said first switch MOSFET; and

a second step of transferring the first voltage on said first voltage line to said circuit through said second switch MOSFET after execution of said first step.

27. A method of activating a semiconductor integrated circuit device according to claim 26, further comprising a third switch MOSFET disposed between said second voltage line and said circuit and a fourth switch MOSFET disposed between said second voltage line and said circuit, said method comprising:

a third step of transferring the second voltage on said second voltage line to said circuit through said third switch MOSFET; and

a fourth step of transferring the second voltage on said second voltage line to said circuit through said fourth switch MOSFET after execution of said third step.

28. A semiconductor integrated circuit device comprising:

a first voltage line supplied with a first voltage;

a second voltage line supplied with a second voltage higher than the first voltage;

a third voltage line;

at least one internal circuit connected to said first voltage line and said third voltage line and activated in response to the voltage on said first voltage line and a voltage on said third voltage line;

a first MOSFET having a source-to-drain path connected between said second voltage line and said third voltage line;

a second MOSFET having a source-to-drain path connected between said second voltage line and said third voltage line; and

a control circuit for controlling said first MOSFET and said second MOSFET, and

wherein a timing provided to change said second MOSFET from an off state to an on state falls behind a timing provided to change said first MOSFET from an off state to an on state and said control circuit controls said first MOSFET so as to be kept in an on state when said second MOSFET changes from the off state to the on state.

29. A semiconductor integrated circuit device according to claim 28, wherein the voltage on said third voltage line is a voltage higher than the first voltage and lower than the second voltage when said internal circuit is in a non-operating state.

30. A semiconductor integrated circuit device according to claim 29, wherein said first MOSFET and said second MOSFET are P channel MOSFETs.

31. A semiconductor integrated circuit device according to claim 30, wherein said first voltage is a ground voltage and said second voltage is a source voltage.

32. A semiconductor integrated circuit device according to claim 31, wherein said internal circuit is composed of CMOSs.

33. A semiconductor integrated circuit device comprising:

a first main voltage line supplied with a first voltage;

a second main voltage line supplied with a second voltage different from the first voltage;

a first sub voltage line supplied with a voltage corresponding to the first voltage;

a second sub voltage line supplied with a voltage corresponding to the first voltage;

a first circuit connected to said first sub voltage line and activated based on the first voltage and the second voltage;

a second circuit connected to said second sub voltage line and activated based on the first voltage and the second voltage;

first MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said first sub voltage line;

second MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said first sub voltage line;

third MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said second sub voltage line;

fourth MOSFETs having source-to-drain paths respectively connected between said first main voltage line and said second sub voltage line;

a first control circuit for controlling said first MOSFET and said second MOSFET; and

a second control circuit for controlling said third MOSFET and said fourth MOSFET, and

wherein a timing provided to change said second MOSFET from an off state to an on state falls behind a timing provided to change said first MOSFET from an off state to an on state and said first control circuit controls said first MOSFET so as to be kept in an on state when said second MOSFET changes from the off state to the on state,

a timing provided to change said third MOSFET from an off state to an on state falls behind the timing provided to change said first MOSFET from the off state to the on state, said first MOSFET is kept in the on state when said third MOSFET changes from the off state to the on state, a timing provided to change said fourth MOSFET from an off state to an on state falls behind the timing provided to change said third MOSFET from the off state to the on state, and said second control circuit controls said third MOSFET so as to be kept in the on state when said fourth MOSFET changes from the off state to the on state.

34. A semiconductor integrated circuit device according to claim 33, further comprising:

a third sub voltage line connected to said first circuit;

a fourth sub voltage line connected to said second circuit;

fifth MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said third sub voltage line;

sixth MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said third sub voltage line;

seventh MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said fourth sub voltage line;

eighth MOSFETs having source-to-drain paths respectively connected between said second main voltage line and said fourth sub voltage line;

a third control circuit for controlling said fifth and sixth MOSFETs; and

a fourth control circuit for controlling said seventh and eighth MOSFETs, and

wherein a timing provided to change said sixth MOSFET from an off state to an on state falls behind a timing provided to change said fifth MOSFET from an off state to an on state and said third control circuit controls said fifth MOSFET so as to be kept in an on state when said sixth MOSFET changes from the off state to the on state,

a timing provided to change said seventh MOSFET from an off state to an on state falls behind the timing provided to change said fifth MOSFET from the off state to the on state, said fifth MOSFET is kept in the on state when said seventh MOSFET changes from the off state to the on state, a timing provided to change said eighth MOSFET from an off state to an on state falls behind the timing provided to change said seventh MOSFET from the off state to the on state, and said fourth control circuit controls said seventh MOSFET so as to be kept in the on state when said eighth MOSFET changes from the off state to the on state.

35. A semiconductor integrated circuit device according to claim 34, wherein the voltage on said third sub voltage line is a voltage higher than the first voltage and lower than the second voltage when said first circuit is in a non-operating state.

36. A semiconductor integrated circuit device according to claim 34, wherein the voltage on said fourth sub voltage line is a voltage higher than the first voltage and lower than the second voltage when said second circuit is in a non-operating state.

37. A semiconductor integrated circuit device according to claim 36, wherein said first, second, third and fourth MOSFETs are N channel MOSFETs.

38. A semiconductor integrated circuit device according to claim 37, wherein said fifth, sixth, seventh and eighth MOSFETs are P channel MOSFETs.

39. A semiconductor integrated circuit device according to claim 38, wherein said first voltage is a ground voltage and said second voltage is a source voltage.

40. A semiconductor integrated circuit device according to claim 39, wherein said first, second, third and fourth circuits are respectively composed of CMOSs.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit device and a method of operating it, and principally to a technique effective for use in a digital integrated circuit device such as a dynamic RAM (Random Access Memory) comprising CMOS circuits each composed of low threshold-voltage type MOSFETs and in a method of operating the digital integrated circuit device.

MOSFETs experience reduced withstand voltage with increased micronization. It is therefore necessary to reduce the operating voltage of a circuit composed of the MOSFETs shaped in micro form. Since a gate voltage supplied to the gate of each MOSFET is also lowered in this case, it is necessary to reduce the threshold voltage provides for flow of a desired current. voltage of the MOSFET so that even the lowered gate However, when the threshold voltage is reduced, a leakage current (hereinafter called a "subthreshold leakage current"), which flows when each MOSFET is brought into an off state, in which the gate and source thereof are equal in voltage to each other, increases exponentially. Thus, even in the case of a CMOS circuit, current consumption at the time of its deactivation increases.

A circuit for reducing the subthreshold leakage current referred to above has been disclosed in Japanese Patent Application Laid-Open Nos. 6(1994)-237164 and 8(1996)-83487 and U.S. Pat Nos. 5,274,601 and 5,408,144 by way of illustrative example. As a method of reducing the leakage current using such a circuit, a CMOS inverter circuit wherein, the time that an input thereof received during its non-operation and an output thereof have been determined as a high level and a low level, respectively, will be described by way of example. In this case, a P channel MOSFET of the CMOS inverter circuit is in an off state and an N channel MOSFET thereof is in an on state. A leakage current produced in the CMOS inverter circuit is determined depending on the subthreshold leakage current of the turned-off P channel MOSFET.

A P channel power switch MOSFET is provided between an operating voltage node connected to the source of the P channel MOSFET of the CMOS inverter circuit and a power line and is turned off upon non-operation. In doing so, the potential at each internal power line placed in a floating state is reduced by the subthreshold leakage current. When the potential is reduced to a some extent, a reverse bias voltage is applied between the gate and source of the P channel MOSFET of the CMOS circuit so that the subthreshold leakage current can be substantially eliminated.

SUMMARY OF THE INVENTION

The inventors of the present application have discussed the application of a method of reducing a subthreshold leakage current to a dynamic RAM. In this case, the present inventors have found various problems which need to be solved to avoid sacrificing the operating speed of the dynamic RAM and to effectively reduce the subthreshold leakage current. Namely, an internal power switch MOSFET is turned off upon standby to reduce the subthreshold leakage current and is turned on upon memory access. In doing so, a pulse-shaped large current will flow when a control signal for changing such a MOSFET from the off state to the on state rises and the power node of the internal circuit is charged up in response to the turning on of the MOSFET. This pulsating current will increase the value of the peak current of a semiconductor integrated circuit device. Upon mounting of such a system, the current capacity of the power device must be increased so as to correspond to the peak value.

The increase in the circuit function and circuit scale of the semiconductor integrated circuit device and the reduction in its source voltage with the device micronization as described above tends toward a size reduction of a system including the device such as a portable electronic device or the like. A battery is also expected to be inevitably used as the power supply. However, the increase in peak current offers a large problem as viewed from the power device of the system, which needs its size reduced. Even in the case of the semiconductor integrated circuit device, large noise is produced in the power line with the occurrence of the peak current referred to above, and hence the operating margin thereof is made worse.

An object of the present invention is to provide a semiconductor integrated circuit device which is capable of realizing less power consumption while ensuring its operating margin. Another object of the present invention is to provide a semiconductor integrated circuit device capable of realizing high integration, a voltage reduction and less power consumption without sacrificing its operating speed.

The above and other objects, novel features and advantages of the present invention will become apparent from the following description and the appended claims of the present specification, taken in conjunction with the accompanying drawings in which preferred embodiments of the present invention are shown by way of illustrative example.

A summary of a typical one of the inventive features disclosed in the present application will be described in brief as follows. A plurality of switch MOSFETs are provided in parallel between internal power lines for a plurality of circuit blocks divided for respective functions and respectively set so as to perform circuit operations in response to operation control signals and a power line for delivering an operating voltage supplied from an external terminal. These switch MOSFETs are turned on in domino or stepwise fashion in response to control signals produced by successively delaying the operation control signals, so as to provide the supply of operating voltages.

A summary of another typical one of the inventive features disclosed in the present application will be described in brief as follows. A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are turned on in domino or stepwise fashion in response to control signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described with reference to the accompanying drawings wherein:

FIG. 1 is a block diagram principally showing examples of an input unit, an X-system circuit and an array block employed in a dynamic RAM to which the present invention is applied;

FIG. 2 is a block diagram principally illustrating examples of a Y-system and write circuit and an output buffer employed in the dynamic RAM to which the present invention is applied;

FIG. 3 is a circuit diagram showing one example of an X-system address input unit employed in the dynamic RAM to which the present invention is applied;

FIG. 4 is a circuit diagram depicting one example of a predecoder supplied with an internal address signal, which is employed in the dynamic RAM to which the present invention is applied;

FIG. 5 is a circuit diagram specifically showing examples of an X decoder, and a latch circuit and a word driver connected thereto, which are employed in the dynamic RAM to which the present invention is applied;

FIG. 6 is a circuit diagram illustrating one example of a mat control circuit employed in the dynamic RAM to which the present invention is applied;

FIG. 7 is a timing chart for describing one example of the operation of the dynamic RAM to which the present invention is applied;

FIG. 8 is a block diagram showing examples of a memory array and its peripheral circuits employed in the dynamic RAM to which the present invention is applied;

FIG. 9 is a block diagram depicting examples of an input/output interface and a timing control circuit employed in the dynamic RAM to which the present invention is applied;

FIG. 10 is a fragmentary circuit diagram showing one example of a memory array employed in the dynamic RAM according to the present invention;

FIG. 11 is a cross-sectional view showing, as one example, a device structure for describing the dynamic RAM according to the present invention;

FIG. 12 is a block diagram for describing one embodiment of a semiconductor integrated circuit device according to the present invention;

FIG. 13 is a block diagram for explaining another embodiment of the semiconductor integrated circuit device according to the present invention;

FIG. 14 is a circuit diagram showing one example of an X-system input unit employed in the dynamic RAM according to the present invention;

FIG. 15 is a timing chart for describing one example of the operation of the X-system input unit shown in FIG. 14;

FIGS. 16A and 16B are respectively schematic structural sectional views showing examples of MOSFETs employed in the semiconductor integrated circuit device according to the present invention;

FIG. 17 is a characteristic diagram illustrating the relationship between a gate length of an N channel MOSFET and its threshold voltage to describe the present invention;

FIG. 18 is a characteristic diagram showing the relationship between a peak current, a delay time of a switch MOSFET start signal and the like;

FIG. 19 is a circuit diagram illustrating another embodiment of the present invention;

FIG. 20 is a timing chart for describing the operation of the embodiment shown in FIG. 19;

FIG. 21 is a system block diagram showing one example of a one-chip microcomputer to which the present invention is applied; and

FIG. 22 is a circuit diagram illustrating a portion of the circuit shown in FIG. 14 formed by MOSFETs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

FIGS. 1 and 2 are block diagrams showing one embodiment of a dynamic RAM to which the present invention is applied. FIG. 1 principally illustrates an input unit, an X-system circuit and an array block. FIG. 2 shows a Y-system and write circuit and an output buffer. In the same drawings, signal transfer paths employed in the present dynamic RAM do not faithfully correspond to signal transfer paths as described in the normal circuit blocks to provide easy understanding of the present invention. Further, the same drawings are mainly plotted from the viewpoint of the supply of an operating voltage to each circuit block.

The dynamic RAM according to the present embodiment is roughly divided into circuits each placed in a state of being supplied with power at all times from the relationship with the outside, for example, as in an input unit and an output (circuit) unit, such as an output buffer or the like, and internal circuits other than the circuits referred to above. Therefore, the respective circuits, which constitute the above-described input unit, and an output circuit typified by an output buffer and a circuit having the need for a memory operation, of the internal circuits, are respectively electrically connected to a source voltage VCC supplied from an external terminal and a circuit ground potential VSS.

On the other hand, each internal circuit for forming a low-level output signal when a memory in a CMOS circuit is in a non-operating state, in other words, in a standby state to reduce a subthreshold leakage current, has a source voltage side electrically connected to sub power lines or sub voltage interconnections or wires (first internal power line). Further, each internal circuit for forming a high-level output signal has a ground side electrically connected to subground lines (second internal power line).

In the present embodiment, the internal circuits are roughly classified into a X-system circuit and a Y-system circuit to reduce a peak current at the time of the supply of the voltage to each above-described internal power line without sacrificing a substantial operating speed. This is because they are different in operating timing from each other. Further, the X-system circuit is further separated into two portions, including an X-system circuit for forming a word line select signal and a portion (circuit portion) provided within the array block, for forming a word-line select signal.

The sub power lines are classified into VCTX, VCTA and VCTY according to the division of the internal blocks as described above, and the subground lines are separated into VSTX, VSTA and VSTY. Although not restricted in particular, a plurality of P channel switches MOSFETS QP1 and QP2, and QP3 and QP4 are respectively provided in parallel between the sub power line VCTX and the power line VCC and between the sub power line VCTA and the power line VCC. Although not limited in particular, a plurality of N channel switches MOSFETs QN1 and QN2, and QN3 and QN4 are respectively provided in parallel between the subground line VSTX and the ground line (first main voltage interconnection or wire) VSS and between the subground line VSTA and the ground line VSS.

These P channel and N channel switches MOSFETs divided into pairs are respectively supplied with control signals .phi.XB and .phi.X, and .phi.AB and .phi.A. These control signals .phi.XB and .phi.X, and .phi.AB and .phi.A are shifted in timing. The control signals .phi.XB and .phi.X are generated in relatively quick timing in association with their operation sequences. The control signals .phi.AB and .phi.A are generated with a relatively slow timing.

The control signal .phi.XB is not supplied in common to the gates of the P channel switches MOSFETs QP1 and QP2, which are provided between the sub power line VCTX and the power line (second main voltage interconnection or wire) VCC associated with the above-described X-system circuit and which are connected to one another in parallel. Namely, the control signal .phi.XB is supplied to the MOSFET QP1 corresponding to the input side and a signal obtained by delaying the same control signal through a delay circuit (control circuit) 17a is supplied to the MOSFET QP2 corresponding to the output side. In the same drawing, the two switches MOSFETs QP1 and QP2 are typically illustrated by way of example. However, the X-system circuit is composed of multistage logic circuits which constitute an X predecoder 6, a mat select circuit 7, an X address comparator 8 for making a comparison between redundant addresses, a mat control circuit 9, etc.

The sub power line VCTX for supplying an operating voltage to these logic circuits extends along a circuit area where it is formed. Therefore, a number of switch MOSFETs such as the switches MOSFETs QP1 and QP2 are provided in parallel form between the sub power line VCTX and the power line VCC so as to provide a desired current supply ability by their composite conductance. In other words, one switch MOSFET is formed into a relatively small size in such a manner that the current supply ability required to activate the X-system circuit can be shared between the plurality of MOSFETs and realized by them.

In the same manner as described above, the control signal .phi.X is not supplied in common to the gates of the N channel switches MOSFETs QN1 and QN2, which are provided between the subground line VSTX and the ground line VSS associated with the above-described X-system circuit and which are connected to one another in parallel. Namely, the control signal .phi.X is supplied to the MOSFET QN1 corresponding to the input side and a signal obtained by delaying the same control signal through a delay circuit 17c is supplied to the MOSFET QN2 corresponding to the output side. Even in the case of the switches MOSFETs QN1 and QN2, in a manner similar to the MOSFETs QP1 and QP2, a number of MOSFETs are provided in parallel between the subground line VSTX and the ground line VSS so as to provide a desired current supply ability by their composite conductance.

Such a switch MOSFET division can bring about the following advantages. One of them is that since the switches MOSFETs are respectively dispersed and formed between the power line VCC and the sub power line VCTX and between the subground line VSTX and the ground line VSS, the degree of freedom of the layout of these MOSFETs can be increased. Namely, the degree of freedom thereof can be realized by suitably providing relatively small MOSFETs within spaces defined between the former two lines and between the latter two lines. By successively activating these MOSFETs in a domino mode, they can be directly driven by relatively small inverter circuits or inverters respectively constituting the delay circuits 17a and 17c, so that a drive current supplied to the gate of each switch MOSFET is dispersed so as to control or suppress the peak current.

Similarly, since the switches MOSFETs are reduced in size, the value of current that flows when each switch MOSFET is turned on, is rendered relatively small, and the switches MOSFETs are successively turned on in the domino mode, the current, which flows in each internal circuit in the X-system circuit, can be also dispersed on a time basis so as to suppress the peak current. By determining the order of activating the MOSFETs in the domino mode in line with a signal transfer mode, the signal can be transferred with satisfactory efficiency by less current as will be described later.

The P channel switches MOSFETs QP3 and QP4 provided between the sub power line VCTA and the power line VCC are provided so as to correspond to the array block, and the N channel switches MOSFETs QN3 and QN4 provided between the subground line VSTA and the ground line VSS are also configured in the same manner as described above. Further, the switches MOSFETs QP3 and QP4 and QN3 and QN4 are switch-controlled on a stepwise basis by the control signals .phi.AB and .phi.A generated with a delay, the delay signals being produced by delay circuits 17b and 17d.

The array block comprises an X decoder 12, a memory array 15, a word driver 13 and a sense amplifier 14. One memory mat is composed of a combination of the memory array 15, the X decoder 12 and the sense amplifier 14 and hence a plurality of memory m