Automatic path delay compensation system

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FIELD OF THE INVENTION

This invention generally relates to an apparatus and method for automatically compensating for path propagation delay in an open-loop system. Specifically, the invention is directed to a system that will automatically compensate for propagation delays resulting from interconnecting cables of varying lengths.

The invention is related to the cable connector of the type described in copending U.S. patent application entitled "Cable Connector Keying" by David Weiss and John R. Klimek, the applicants herein, filed Dec. 15, 1992 as U.S. patent application Ser. No. 07/990,738, now U.S. Pat. No. 5,559,964, and the compensation scheme described in copending U.S. patent application entitled "Path Delay Compensation in an Open-Loop System" by David Weiss and John R. Klimek, the applicants herein, filed Dec. 21, 1992 as U.S. patent application Ser. No. 07/994,392. Both of the foregoing applications are assigned to the same assignee as the present patent application and the details of both are incorporated herein by reference.

BACKGROUND OF THE INVENTION

When interconnecting components in an open-loop system, one must provide a means of coordinating communications between the components. Some systems, for example, require that data from one component be received at another component at a specific point in time relative to a system clock. Because of the propagation delay experienced by the data in traveling between the components, one has to account for that delay on the receiving end. When the path delay is variable, for example where the path is a cable and the user desires to change cable lengths to suit the particular application, the accompanying variation in propagation time must be taken into consideration.

It would be helpful to provide a way of communicating such information without having to physically program a module or an EPROM, or manipulate jumpers. Ideally, the information would be conveyed in an automatic and transparent manner.

SUMMARY OF THE INVENTION

These and other objects are achieved by a system that uses information encoded in a connecting cable to adjust the time of transmission of data to cause that data to arrive at a connected component at a fixed time relative to a system clock signal. In one embodiment, the encoding is contained in a keyed cable that automatically conveys the delay of the cable to the interconnected unit. The encoding occurs during the manufacture of the cable, and the information transfer occurs when the cable is plugged into an operating system automatically configuring the system. Thus, the system automatically compensates for cable delay without the need for any further adjustments.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention, as well as other objects and advantages thereof not enumerated herein, will become apparent upon consideration of the following detailed description and the accompanying drawings, wherein:

FIG. 1 is a schematic block diagram of a system incorporating the invention;

FIG. 2 is a schematic block diagram of the phase shift module;

FIG. 3 is a schematic block diagram of the phase-locked loop circuit;

FIG. 4 is a schematic block diagram of the variable clock-shift module;

FIG. 5 is a timing diagram showing the outputs of the multiplexer in the variable clock-shift module;

FIG. 6 is a schematic block diagram of the bit delay module; and

FIG. 7 is a schematic block diagram of the remote module, the encoder, and the decoder.

DETAILED DESCRIPTION OF THE INVENTION

A block diagram of a communication system is shown in FIG. 1. The system has two communications units, arbitrarily labeled local 10 and remote 30, interconnected by a cable 48. The cable 48 has a connector 50 that mates with a socket 52 on the remote unit 30. Internally, the connector 50 has an encoder 54 that electrically mates with a decoder 56 in the remote unit 30. The decoder 56 is distributed across the socket 52 and a portion of the remote unit 30.

The local unit 10 and the remote unit 30 each have a transmitter-receiver 12, 32. The transmitter-receivers 12, 32 each have a transmit port 14, 34, a receive port 16, 36, a transmit clock input 18, 38, and a receive clock input 20, 40.

The local unit 10 has three ports: the transmit port 14 and the receive port 16 of the transmitter-receiver 12, and a local clock port 22. A clock 24 provides a local clock signal on local timing line 26 to the transmit and receive clock inputs 18 and 20 of the transmitter-receiver 12. The clock signal output is also provided for transmission to the remote unit 30 at the local clock port 22.

The remote unit 30 also has three ports: the transmit port 34 and the receive port 36 of the transmitter-receiver 32, and a remote clock port 42. The remote unit 30 has a phase shift module 60 having an input 62 and an output 64. The input 62 is connected to the remote clock port 42 by an input clock line 66 and the output 64 is connected to a remote timing line 68, which in turn provides transmit timing to the transmitter-receiver 32 through its transmit clock input 38. The input clock line 66 is also connected to the receive clock input 40 of the transmitter-receiver 32. Finally, the phase shift module 60 has a select input 70 from the decoder 56.

The local and remote units 10 and 30 are interconnected by a transmission path, in the case illustrated in FIG. 1 the path being a cable 48. The cable 48 has two unidirectional transmission lines 72 and 74, which may carry data in serial, parallel, or some other form (digital, analog, etc.), and a unidirectional synchronization clock line 76. Line 72 interconnects the transmit port 34 in the remote unit 30 with the receive port 16 in the local unit 10. Similarly, line 74 interconnects the transmit port 14 in the local unit 10 with the receive port 36 in the remote unit 30.

The synchronization clock line 76, being connected between the local clock port 22 and the remote clock port 42, provides the remote unit 30 with the clock timing signal generated in the clock 24 of the local unit 10. The cable 48 could well have other lines but they are not illustrated here. Because a timing signal is not returned with the data, the system is characterized as open-loop.

The Phase Shift Module

As shown in FIG. 2, the phase shift module 60 has a phase-locked loop 80 feeding a variable clock-shift module 82 through line 84. The phase-locked loop 80, shown in greater detail in FIG. 3, has a comparator 90, a voltage-controlled oscillator 92, and a divide-by-n counter 94, interconnected by lines 96, 98, and 100 as shown in the figure.

The variable clock-shift module 82 is shown in FIG. 4. The module 82 divides an input clock signal of frequency nf into 2.sup.d selectable pulses at a intervals over some period .tau. (=a/nf), where a.gtoreq.d, each of which has a different phase relationship with respect to each other. The input (line 84) to the module 82 is connected to a divide-by-a counter 110 having b outputs, Q.sub.1 through Q.sub.b, where a.gtoreq.log.sub.2 b in a binary system. These b outputs are connected by lines 112 to corresponding inputs 1 through b of a b-to-c decoder 114. The outputs 1 through c of the decoder 114 are connected in turn by lines 116 to inputs 1 through 2.sup.d of a 2.sup.d -to-1 multiplexer 118, respectively.

The multiplexer 118 is controlled by select lines 122 connected to select inputs S.sub.1 through S.sub.d, and its output is connected to the D input of a D-type tip-flop 124. The clock signal for the tip-flop 124 is provided on a clock input line 126 tied to line 84. The output of the module 82 is the Q output of the flip-flop 124, which is also the output 64 of the phase shift module 60. An example of the selectable outputs MUX1-MUX8 of the multiplexer 118 is illustrated by the timing diagram in FIG. 5, which assumes a division-by-8 of the clock signal on line 84.

For simplicity of presentation, there is a one-to-one correspondence between the respective interconnections of the counter 110, the decoder 114, and the multiplexer 118. However, it should be understood that this is not required and one may choose to omit and/or transpose selected connections to suit individual design needs.

The Whole-Bit Data Shift Module

An additional shift can be obtained from the bit-shifting module 140. This component can be inserted, for example, within the transmitter-receiver 32 at the transmit port 34 in the remote unit 30. The purpose of the bit-shifting module 140 is to adjust the time of transmission of the data in some selected number of whole-bit increments, as determined by the user.

As shown in FIG. 6, the bit-shifting module 140 is a series of p cascaded D-type flip-flops 142, having a data input 148 connected to the D input of the first flip-flop FF1 142. The Q output of every flip-flop 142 but the last is tied to the D input of the next device. The clock input is derived from the output of the phase shift module 60 on line 68. The data input 148 and the Q outputs of the flip-flops are also provided by lines 152 as inputs to a q-to-1 multiplexer 144, where q=p+1. The multiplexer 144 is controlled by z select lines 146 connected to select inputs S.sub.1 through S.sub.z, to provide an output 150.

The Encoder and Decoder

As illustrated in FIGS. 1 and 7, the cable 48 is attached to a connector 50 that mates with a socket 52 on the remote unit 30. For purposes of clarity, the encoder 54 and the decoder 56 are shown as lightly-shaded boxes, to allow the reader to easily distinguish these components from the rest of the circuitry in FIG. 7. Further, although only one connector/socket combination is illustrated in FIG. 1, it should be understood that the cable 48 could have the same arrangement at each end, irrespective of whether the mating socket has a decoder.

The connector 50, the socket 52, the encoder 54, the decoder 56, and the remote unit 30 are shown schematically in FIG. 7. In addition to the functional pins 160, 162, and 164 connected to the unidirectional transmission lines 72 and 74, and the unidirectional synchronization clock line 76, respectively, and any other j functional pins not illustrated here, the connector 50 has four pins 170, 172, 174, and 176, as shown in the shaded portion of FIG. 7. Correspondingly, the socket 52 has four pins 180, 182, 184, and 186. The number four is arbitrary and used for illustration purposes only; one would provide k+1 pins to convey up to 2.sup.k combinatorial code words. The number k in the expression k+1 can be any number greater than or equal to 1. The four pins shown in FIG. 7 will provide up to 8 code words of three bits each. The other j pins could carry dam or other functional information conveyed through the cable 48.

On the remote unit 30 side, one pin 186 is connected to ground 188. The remaining three pins 180, 182, and 184 are connected to key lines 190, 192, and 194. The key lines 190, 192, and 194 are connected through pull-up resistors 196 to some potential shown in FIG 7 as voltage V.sub.CC 198. Note that the device could employ pull-down resistors instead of pull-up resistors, connecting key lines 190, 192, and 194 through resistors to ground 188 and pin 186 to V.sub.CC 198.

Operation of the System

Consider bidirectional communications between the local and remote units 10 and 30. The local unit 10 transmits data along line 74 to the remote unit 30 along with a synchronizing clock signal on line 76. When the data arrives at the transmitter-receiver 32 in the remote unit 30, it is docked in by the received clock signal applied to receive clock port 40.

To send data from the remote unit 30 to the local unit 10, the timing must now be coordinated as the local unit 10 will be looking for the data at a precise point in time T.sub.D relative to the synchronizing signal (line 26) at the receive clock input 20. This represents the total round trip delay from the local unit 10 to the remote unit 30 and back again.

To achieve a transfer within this period of time, one must account for the propagation delay time of the cable (T.sub.C each way) and the propagation delay of the electronics of the remote unit 30 (D.sub.E). Given that a round trip entails passage of the synchronizing clock signal through the cable 48 to the remote unit 30, and then passage of the data through the remote unit 30 and onto and through the cable 48 to the local unit 10, the total delay time T.sub.D will be 2.multidot.T.sub.C +D.sub.E. The quantity T.sub.D is selected to allow for the largest required round trip transit time.

Since changes in path delay between the units 10 and 30 (denoted as T.sub.C ') would result in variations in total propagation time, a variable quantity T.sub.S is utilized to achieve a constant T.sub.D, where:

2.multidot.T.sub.C '+D.sub.E +T.sub.S =T.sub.D. (1)

The time interval T.sub.S represents the shift in time of the data that must occur in the remote unit 30 so that the data is received at the local unit in an elapsed time of T.sub.D.

The time shift T.sub.S would have possibly one, two, or more components. The first component is T.sub.Sf, the fractional bit time shift. Depending on the desired granularity, one could shift the timing of the transmit clock signal at transmit clock input 38 in the remote unit 30 by some fractional portion of one bit length, as illustrated in FIG. 5 using the circuit of FIG. 4, effectively time shifting the data an equivalent amount.

The second component is T.sub.Sb, the whole bit time shift of the data (FIG. 6). This affords a time shift greater than T.sub.Sf. If desired, one could achieve a greater delay by shifting larger units, such as a byte of data. Therefore, the total shift T.sub.S would be the sum of T.sub.Sf, T.sub.Sb, and perhaps a further component. Given that

T.sub.D =2.multidot.T.sub.C '+D.sub.E +T.sub.S (2)

and, assuming only two components of shift:

T.sub.D =2'T.sub.C '+D.sub.E +T.sub.Sf +T.sub.Sb (3)

Since T.sub.D and D.sub.E are fixed numbers, and the value of T.sub.C ' is determined by the path delay through the cable 48, one can thus calculate T.sub.Sf and, if need be, T.sub.Sb. In most applications, insertion of the T.sub.Sf component will be sufficient. Where a greater delay is desired, one may have to resort to T.sub.Sb. Therefore:

T.sub.Sf +T.sub.Sb =T.sub.D -(2.multidot.T.sub.C '+D.sub.E)(4)

The exact values of T.sub.Sf and T.sub.Sb are set by asserting the select lines 122 and 146 of the 2.sup.d -to-1 multiplexer 118 and the q-to-1 multiplexer 144, respectively. To perform the selection in the outputs of the multiplexers 118 and 144, the appropriate select lines 122 and 146 would be connected to ground or V.sub.CC, as required. It should be understood that one could use T.sub.Sb independently of T.sub.Sf if whole-bit manipulation would provide sufficient resolution. Moreover, if no shift is desired, one could select either an unshifted multiplexer output signal (MUX1 in FIG. 5) or the signal on the input clock line 66. The latter could be provided directly to the transmit clock input 38, bypassing the phase shift module 60.

As shown in FIG. 7, pins 170 and 174 are connected by wires 200 and 202, respectively, to pin 176. Before the connector 50 is inserted into the socket 52, the key lines 190, 192, and 194 are all sitting at V.sub.CC. The binary code word 111 can conveniently be used to automatically detect that a cable is not connected at all. When the connector 50 is inserted into the socket 52 as illustrated in FIG. 7, one path is created from key line 190 through pin 180, pin 170, wire 200, pin 176, and pin 186 to ground 188. Similarly, another path is created from key line 194 through pin 184, pin 174, wire 202, pin 176, and pin 186 to ground 188. Now, key lines 190 and 194 are at ground potential and only key line 192 remains at V.sub.CC. The information thus conveyed is 010. By changing the arrangement of the wires within the encoder 54, adding, subtracting, or reordering them, the information would likewise be changed.

The three key lines 190, 192, and 194 are connected to multiplexer select lines 122 (in FIG. 4; 70 in FIG. 1). By inserting the connector 50 into the socket 52, the multiplexer 118 will select one of its 2.sup.d inputs. Similarly, additional pins and key lines could be provided to control the select lines 146 of the circuit of FIG. 6, if a whole-bit shift of the data is sought. As noted earlier, the circuit of FIG. 6 may be employed in addition or instead of the scheme of FIG. 4.

Therefore, when the connector 50 is inserted into the socket 52, the encoder 54 and the decoder 56 mate, and the configuration information is passed automatically; enabling the remote unit 30 to transmit data such that it arrives at the local unit 10 at the proper time.

It should be understood that the local and remote clocks may differ in frequency and duty cycle as required by the particular implementation. Also, the transmit data rates and the synchronization clock frequency may differ. Moreover, this scheme can be used with systems having more than two components. For example, where there are three or more communications modules connected in a system, the same method of adjusting the transmit time relative to a clock at the ultimate destination will serve to insure that data arrives at the receiving module at the proper time.

While there has been described what is believed to be the preferred embodiment of the invention, those skilled in the art will recognize that other and further modifications may be made thereto without departing from the spirit of the invention, and it is intended to claim all such embodiments that fall within the true scope of the invention.

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