A bus monitor system comprises eight identical programmable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to the event bus within each monitor circuit. One interface asserts a predetermined bit pattern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pattern stored in a monitor circuit register. A third interface asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an external pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit interfaces. If any asserted bit on the event bus matches a corresponding bit of one of the predetermined bit patterns stored in the interface enable and disable registers, that interface will be enabled or disabled, respectively. The event bus gives the monitor system the ability to simultaneously monitor for multiple bit patterns on the monitored bus, and to monitor for a sequence of bit patterns by having one monitor circuit trigger another.
The circuit to be used either to create a simultaneously switching outputs (SSO) event or to create a simultaneously switching inputs (SSI) event. The circuit uses a toggle register to generate a toggling signal and a signal line to operate logic to select the toggling signal as output from the circuit for the SSO event. The signal line is connected to an external pin. The circuit uses another signal line, also connected to an external pin, to disable or tristate the output driver that drives the I/O pin. This permits the circuit to receive input for the SSI event. Two chips, each having a plurality of such circuits, can be arranged so that one chip generates the SSO event and sends it to the second chip, which is configured to receive the SSI event. The circuit also has a pair of registers in a cascade arrangement to provide precise control of the output signal. The circuit has an additional register to disable the output driver and permit the circuit to receive input for a scan event.
A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device. In providing the data optimization attributes external to the microcontroller, the data optimization attribute may be temporarily held by trace pins of a debug port of the microcontroller. The data optimization attributes may be extracted from the object information signal and processed by the external trace capture equipment or the bus monitoring device. By processing the data optimization attributes, pre-optimization write object values may be reconstructed.
A data stream is transferred through a parallel data bus while the read or write strobe is adjusted. The resultant data is compared to the original data to detect errors with each data line of the parallel bus. The results are displayed on a grid whereby the characteristics of each line of the data bus may be visually understood. The characteristic image of the performance of the data bus may be used for debugging the bus, as well as for other uses wherein the performance is very highly characterized.
An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.
An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel. In response to the data indicative of the monitored event, the CPU circuit reconfigures the reconfigurable circuit to monitor for another event type occurring on the communication channel and thereby permits for an adaptive evaluation of the communication channel. Another aspect of the invention is directed to the CPU redirecting data communication in response to this adaptive evaluation.
