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Claims  |
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We claim:
1. A method for testing a ball grid array semiconductor device comprising
the steps of:
providing a semiconductor device having a substrate with a periphery, a
plurality of conductive vias formed in the substrate, a semiconductor die
mounted on the substrate and electrically coupled to the plurality of
conductive vias, a plurality of conductive balls attached to the substrate
and electrically coupled to the semiconductor die through the plurality of
conductive vias, and a plurality of conductive castellations formed around
the periphery of the substrate and electrically coupled to the
semiconductor die, wherein each conductive ball of the plurality of
conductive balls has an associated conductive castellation of the
plurality of conductive castellations and wherein the associated
conductive castellation of the each conductive ball has an associated
conductive via of the plurality of conductive vias;
providing a test socket for receiving the semiconductor device and having a
plurality of test contacts;
placing the semiconductor device in the test socket such that the plurality
of test contacts is electrically and physically in contact with the
plurality of conductive castellations and without being in physical
contact with the plurality of conductive balls; and
biasing the semiconductor device using the plurality of test contacts and
the plurality of conductive castellations to send at least power to the
semiconductor die without the plurality of test contacts physically
contacting the plurality of conductive balls.
2. The method of claim 1 wherein the step of biasing is performed at a
temperature above an ambient temperature.
3. The method of claim 2 wherein the step of biasing comprises burning-in
the semiconductor device.
4. The method of claim 3 wherein the step of biasing comprises burning-in
the semiconductor device at a temperature within 50.degree. C. of a
melting point of the plurality of conductive balls.
5. The method of claim 1 wherein the step of biasing comprises functionally
testing the semiconductor device.
6. The method of claim 1 wherein the step of biasing comprises testing the
semiconductor device for open circuits and testing the semiconductor
device for short circuits.
7. The method of claim 1 wherein the steps of providing a semiconductor
device comprises providing a semiconductor device wherein the associated
conductive via and the associated conductive castellation are associated
exclusively.
8. A method for testing a ball grid array semiconductor device comprising
the steps of:
providing a substrate having a top surface, a bottom surface, periphery, a
first plurality of conductive traces formed on the top surface, a second
plurality of conductive traces formed on the bottom surface, a plurality
of vias extending through the substrate, and a plurality of conductive
contact portions formed around the periphery of the substrate, wherein
each via of the plurality of vias is used to electrically connect a
conductive trace from the first plurality of conductive traces on the top
surface to an associated conductive trace of the second plurality of
conductive traces on the bottom surface, and wherein for each via of the
plurality of vias there is an associated conductive contact portion of the
plurality of conductive contact portions electrically connected thereto,
and wherein each contact portion is physically distinguishable from the
first and the second pluralities of conductive traces;
providing a semiconductor die mounted to the top surface of the substrate
and electrically connected to the first plurality of conductive traces;
providing a plurality of conductive balls attached to the bottom surface of
the substrate and electrically connected to the second plurality of
conductive traces;
providing a test socket having a plurality of test contacts configured to
be able to physically and electrically contact the plurality of conductive
test contacts without physically contacting the plurality of conductive
balls;
placing the substrate with the semiconductor die mounted thereto and the
plurality of conductive balls attached thereto into the test socket such
that the plurality of test contacts is in physical and electrical contact
with the plurality of conductive contact portions and without being in
physical contact with the plurality of conductive balls; and
exercising the semiconductor die at a temperature in excess of 50.degree.
C. by sending electrical signals to the semiconductor die using the
plurality of test contacts without the plurality of test contacts
physically contacting the plurality of conductive balls.
9. The method of claim 8 wherein the step of exercising comprises
burning-in the semiconductor die.
10. The method of claim 8 wherein the step of exercising comprises
functionally testing the semiconductor die.
11. The method of claim 8 wherein the step of exercising comprises testing
the semiconductor die for open circuits and testing the semiconductor die
for short circuits.
12. The method of claim 8 wherein the step of exercising comprises
exercising the semiconductor die at an ambient temperature wherein the
ambient temperature is within 50.degree. C. of a melting point of the
plurality of conductive balls.
13. The method of claim 12 wherein the step of providing a plurality of
conductive balls comprises providing a plurality of solder balls.
14. The method of claim 8 wherein the step of providing a substrate
comprises providing a substrate wherein the plurality of conductive
contact portions comprises a plurality of conductive contact castellations
formed along the periphery of the substrate.
15. A method of testing a ball grid array semiconductor device comprising
the steps of:
providing a substrate having a plurality of vias, a first plurality of
conductive traces on a first surface, a second plurality of conductive
traces on a second surface opposing the first surface, and a plurality of
edge contacts, wherein each via of the plurality of vias electrically
connects a first conductive trace of the first plurality of conductive
traces to a second conductive trace of the second plurality of conductive
traces and wherein the each via has an exclusively associated edge contact
of the plurality of edge contacts which is electrically connected to the
first conductive trace and the second conductive trace such that the
exclusively associated edge contact is a redundant electrical connection
to the first conductive trace and to the second conductive trace;
providing a semiconductor die mounted to the first surface of the substrate
and electrically connected to the first plurality of conductive traces;
providing a plurality of conductive balls attached to the second surface of
the substrate and electrically connected to the second plurality of
conductive traces;
providing a test socket having a plurality of test contacts;
placing the substrate with the semiconductor die mounted thereto and with
the plurality of conductive balls attached thereto into the test socket;
and
biasing the semiconductor die by physically contacting the plurality of
edge contacts with the plurality of test contacts and applying power to
the semiconductor die without permitting the plurality of test contacts to
physically contact the plurality of conductive balls.
16. The method of claim 15 wherein the step of providing a substrate
comprises providing a substrate wherein the plurality of edge contacts
comprises a plurality of conductive castellations formed along a periphery
of the substrate.
17. The method of claim 15 wherein the step of biasing is performed at a
temperature in excess of 50.degree. C.
18. The method of claim 17 wherein the step of biasing comprises burning-in
the semiconductor die.
19. The method of claim 15 wherein the step of biasing comprises
functionally testing the semiconductor die.
20. The method of claim 15 wherein the step of biasing comprises testing
the semiconductor die for open circuits and testing the semiconductor die
for short circuits.
21. A ball grid array semiconductor device comprising:
a substrate having a periphery, a first plurality of traces, a second
plurality of traces, a plurality of vias which electrically connect the
first plurality of traces to the second plurality of traces, and a
plurality of conductive castellations formed along the periphery, wherein
for each via of the plurality of vias there is one exclusively associated
conductive castellation of the plurality of conductive castellations such
that the each via and its exclusively associated conductive castellation
are redundant electrical connections to a trace of the first plurality of
traces and to a trace of the second plurality of traces;
a semiconductor die mounted to the substrate;
electrical connections between the semiconductor die and the first
plurality of traces; and
a plurality of conductive balls attached to the substrate and electrically
connected to the second plurality of traces, wherein each conductive ball
of the plurality of conductive balls is associated with a via of the
plurality of via and with its exclusively associated conductive
castellation.
22. The ball grid array semiconductor device of claim 21 wherein the
semiconductor die has a plurality of bonding pads as input/output
terminals of the semiconductor die, and wherein the first plurality of
traces includes a trace associated with each bonding pad of the plurality
of bonding pads.
23. The ball grid array semiconductor device of claim 22 wherein the
plurality of bonding pads includes all input/output terminals of the
semiconductor die.
24. The ball grid array semiconductor device of claim 21 wherein the
substrate is an organic substrate.
25. The ball grid array semiconductor device of claim 21 wherein the
plurality of conductive balls comprises a plurality of solder balls.
26. The ball grid array semiconductor device of claim 25 wherein the
plurality of solder balls is made of solder having a composition
approximately that of eutectic solder. |
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Claims |
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Description |
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FIELD OF THE INVENTION
The present invention relates to testing of semiconductor devices, and more
specifically to methods and structures for testing Ball Grid Array
semiconductor devices.
BACKGROUND OF THE INVENTION
Ball Grid Array (BGA) semiconductor devices are quickly becoming an
industry standard package configuration because BGA devices enable a
higher pin count per unit area of a user's board and provide faster
accessing times in a use's system as compared to peripherally leaded
devices. While BGA devices are gaining acceptance, manufacturing issues
with the devices remain which sometimes inhibit their use. Some of these
manufacturing issues affect the reliability or performance of the BGA
device. Other problems relate to the cosmetic appearance of BGA devices.
While a cosmetic problem would seem to be less significant, these problems
can nonetheless be a determining factor in whether a user purchases a BGA
device.
One cosmetic problem affecting BGA semiconductor devices is the shape of
the conductive balls, usually solder balls, which are attached to the
bottom side of a wiring substrate in place of conventionally formed leads.
After solder balls are positioned on the substrate, the device undergoes a
reflow operation which melts the solder and metallurgically joins the
solder balls to metal pads on the BGA device substrate. After reflow, the
balls have a uniform spherical contour due to natural surface tension
forces which act upon the melted solder. It is this uniform spherical ball
shape which a user expects in the final device. However, subsequent
manufacturing operations can slightly change the shape of the ball. While
often times the change in ball shape has no impact on device performance,
the fact that the ball is no longer perfectly round causes a user to
reject the device.
One such manufacturing process which can lead to ball deformation is that
of testing, and particularly testing at elevated temperatures. After the
semiconductor device is manufactured, the device undergoes a variety of
tests to prove its reliability before being sent to the customer. A
conventional method for testing BGA semiconductor devices is through the
use of a pogo pin socket. A finished, assembled device is placed in a
socket wherein spring-loaded pogo pins contact the plurality of solder
balls on the bottom of the device. If the testing is performed at elevated
temperatures, the solder material will soften, more so as the testing
temperature approaches the melting point of the solder ball material. Upon
softening, the force of the pogo pins against the ball will cause the
balls to deform. Once testing is complete and the device returns to
ambient temperature, indentations in the balls due to the pressure of the
pogo pins remain.
One method to fix the deformation in the balls as a result of elevated
temperature testing is to re-heat the device after testing is complete to
a temperature at or above the melting point of the balls. During this
thermal process, the solder balls will reflow, allowing the balls to
re-acquire the spherical shape existent before testing. This post-test
reflow melts the solder ball material causing natural surface tension
forces to produce the desired spherical shape. Upon cooling, each of the
balls will again be dose to perfectly round, meeting the customer's
expectations.
While post-test reflow will remove obvious deformation of the balls, there
are many problems associated with performing a reflow operation after
test. One problem is that the devices may have accumulated moisture, such
that upon reflowing the solder, the moisture vaporizes and causes the
package to crack. To avoid this problem a semiconductor manufacturer might
be required to drive off the moisture content through a lower temperature,
longer cycle heating operation. Another problem is that the solder balls
have a native oxide build-up which affects the ability of the solder
material to reflow uniformly. The oxide inhibits or changes the surface
tension forces on the solder material, causing the balls to have a
wrinkled or raisin-like appearance after reflow. To avoid this problem,
the manufacturer would have to apply a flux to the solder balls to remove
the oxide layer prior to the reflow operation. A third problem with a
reflow process following test is that special handlers for handling
singulated BGA devices would be needed for the device to reflow the balls
after test. Testing is usually accomplished after individual devices have
been singulated from BGA substrate strips, while many processes in the
manufacture of BGA devices are designed to handle substrate strips having
multiple devices. After processing, the devices singulated from the strip
for individual testing. A reflow operation after testing would require
special handlers to be made to accommodate as-singulated devices.
Accordingly, the solution to solder ball deformation which involves a
reflow process after test is not suitable. It requires additional capital
expenditures and additional manufacturing time. Therefore, a need exists
for an improved testing method for BGA devices which alleviates customer's
concerns about deformed conductive balls.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top view of a substrate for use in a BGA semiconductor device
in accordance with the present invention.
FIG. 2 is a magnified view of a portion of the substrate illustrated in
FIG. 1.
FIG. 3 is a view of a bottom surface of the substrate illustrated in FIG.
1.
FIG. 4 is a magnified view of a portion of the bottom surface of the
substrate illustrated in FIG. 1.
FIG. 5 is a partial cross-sectional view of a BGA semiconductor device in
accordance with the present invention.
FIG. 6 is an exploded cross-sectional view of a portion of the peripheral
edge of the substrate illustrated in FIG. 5.
FIG. 7 is a top view of a test socket suitable for testing a BGA
semiconductor device in accordance with the present invention.
FIG. 8 is a cross-sectional illustration of the test socket illustrated in
FIG. 7, wherein the test socket is in a closed position.
FIG. 9 is a cross-sectional illustration of the test socket of FIG. 7,
wherein the test socket is in an open position.
FIG. 10 is a cross-sectional illustration of the test socket of FIGS. 7-9,
as the socket holds a BGA semiconductor device in accordance with the
invention.
FIG. 11 is an exploded view of how the test contacts of the test socket
contact the semiconductor device in accordance with an embodiment of the
present invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Generally, the present invention provides a method for testing a ball grid
array (BGA) semiconductor device wherein the conductive balls attached to
a surface of the substrate are not contacted during a testing operation.
Accordingly, even at elevated testing temperatures, no deformation of the
balls occurs. Testing is accomplished without physically contacting the
balls through the use of a plurality of edge contacts or conductive
castellations which are formed around the periphery of the substrate of
the BGA device. A test socket is designed to engage or contact the
peripheral edge contacts or conductive castellations without contacting
the conductive balls during test. Because no external pressures are
exerted upon the balls during testing, deformation to the balls does not
occur even at elevated temperatures near the melting point of the
conductive balls. A further advantage of practicing the invention is that
since the conductive balls are not contacted, there is no risk that the
balls will melt and fuse to the test contacts, thereby destroying the test
socket as well as the device being tested. Moreover in the case of solder
balls, the need to clean the test sockets to remove solder build-up from
the test contacts is eliminated since the test contacts never come into
contact with the solder balls during the testing operation.
These and other features and advantages of the present event will be more
clearly understood from the following detailed description taken in
conjunction with the accompanying drawings. It is important to point out
that the illustrations are not necessarily drawn to scale, and that there
are likely to be other embodiments of the present invention which are not
specifically illustrated.
FIG. 1 is a top view of a top surface of substrate 10 having a
semiconductor die 12 mounted thereto. Substrate 10 includes a plurality of
conductive traces 14. On the illustrated top surface, one end of each
conductive trace on the top surface terminates into a bonding finger 16.
An opposing end of each conductive trace terminates at a conductive
castellation 18 at the periphery of the substrate. Between the bonding
finger and the conductive castellation associated with each trace is a
conductive via 20.
For each conductive trace on the top surface of substrate 10, there is an
associated bonded finger 16, an associated conductive castellation 18, and
an associated conductive via 20. This associated relationship is more
clearly illustrated in a magnified view of substrate 10 in FIG. 2. As FIG.
2 demonstrates, each of the four traces illustrated has its own bonding
finger, its own conductive castellation, and its own conductive via
associated therewith. For instance, conductive trace 14' has a bonding
finger 16', a conductive castellation 18' and a conductive via 20'
associated therewith, and conductive trace 14" has a bonding finger 16", a
conductive castellation 18" and a conductive via 20" associated therewith.
FIGS. 1 and 2 also illustrates how semiconductor die 12 is electrically
connected to the conductive traces on the top surface of substrate 10.
Specifically, semiconductor die 12 includes a plurality of bonding pads 22
which serve as input/output terminals of the die. As illustrated, bonding
pads 22 are formed around a periphery of semiconductor die 12. The bonding
pads are electrically connected to the integrated circuitry (not shown) of
the semiconductor die in a conventional manner (e.g. through metal layers
and contacts formed in the die). The bonding pads are electrically
connected to conductive traces 14 through the use of wire bonds 24 which
connect bonding pads 22 to bonding fingers 16. Wire bonds 24 are typically
made of a gold or aluminum material and are bonded to the bonding pads and
bonding fingers using conventional techniques. While the electrical
connection between semiconductor die 12 and substrate 10 is herein
described through use of wire bonds, it is important to realize that other
connection mechanisms can also be used in conjunction with the present
invention. For example, flip-chip techniques, such as controlled collapse
chip connection (C4), can be utilized to connect an array of conductive
bumps formed on a chip to an array of bonding fingers or bonding pads on a
substrate.
Substrate 10 as used in accordance with one embodiment of the present
invention can be manufactured using conventional substrate manufacturing
techniques. While the bulk material of this substrate is not limited by
the practice of this invention, it is likely that the most beneficial use
of the present invention is in conjunction with organic substrates, such
as epoxy-based resin substrates, including bismaleimide triazine (BT)
resin. While there is no apparent reason why other substrate materials,
such as ceramics, cannot be used in conjunction with the present
invention, organic substrates are particularly susceptible to deformed
solder balls as a result of testing at elevated temperatures. The
susceptibility of organic substrates is due to the fact that the solder
ball composition used in conjunction with an organic substrate is
typically a eutectic or near-eutectic solder composition (63% tin and 37%
lead) which has a melting point which is lower than other solder
compositions. The melting point for eutectic solder is about 184.degree.
C. Other substrate materials, including ceramic substrates, often utilize
higher temperature solder materials, for example a 97% tin and 3% lead
composition which has a melting point of about 230.degree. C. Accordingly,
elevated testing temperatures at 125.degree.-150.degree. C. will have a
more severe impact in deforming eutectic solder balls as compared to other
compositions. Therefore, organic substrates are more prone to deformed
balls as a result of testing at elevated temperatures.
Rather than specifying the benefits of the present invention based on the
substrate material, perhaps a better correlation is to the actual testing
conditions utilized. For example, the present invention is likely to
benefit any testing operation for BGA devices wherein the testing is
performed above ambient temperature. More specifically, the present
inventions benefits testing performed at or above 50.degree. C., and even
more specifically performed within 50.degree. C. of the melting point of
the conductive ball material. The likelihood that conductive balls will
deform during testing is also a function of time or duration of the test.
The longer the test, the more likely deformation will occur even at lower
temperatures. Accordingly, the present invention can also be related to
testing times. Testing times in excess of one or two minutes will benefit
from practicing the invention, but a larger benefit will be achieved for
testing times in excess of one hour, and even larger for times in excess
of one day.
The formation of conductive traces 14, bonding fingers 16, conductive
castellations 18, and conductive vias 20 can be formed on substrate 10 in
accordance with conventional manufacturing practices. For example, in the
case of organic substrates, each of the conductive members may be formed
by first laminating a conductive layer, for example copper, onto a
dielectric sheet. Following lamination, a lithography process can be used
to mask or pattern the metal layer. The masked metal layer is then etched
to form the desired conductive pattern for the members. Conductive vias 20
and conductive castellations 18 can be formed through conventional
punching or drilling operations to form holes through the substrate either
before or after patterning the metal layer. After drilling or punching the
holes in the substrate are then plated with a conductive material to make
the holes in the substrate conductive throughout. Castellations 18 can be
formed by first forming a conductive via in the substrate (preferably
simultaneously with the formation of vias 20), and then subsequently
excising or cutting the substrate through a row of vias. Stated otherwise,
conductive castellations can be thought of as half-vias, wherein one half
of a via has been removed or cut away, leaving the other half of the via
in place to form the conductive castellation.
FIG. 3 illustrates substrate 10 from a bottom view. The conductive
castellations and conductive vias of FIG. 1 are replicated in FIG. 3, as
these elements extend entirely through the thickness of the substrate. It
is noted, however, that in place of through vias which extend directly
from a top surface to a bottom surface of the substrate, a substrate used
in accordance with the present invention can also or instead utilize blind
or buried vias, particularly in a multi-layer substrate. Buried vias are
vias which are completely internal to the substrate, without extending to
either a top or bottom surface of the substrate, while blind vias are vias
which include one internal end, and one end which extends to either the
top or bottom surface of the substrate.
Also illustrated in FIG. 3 and present on the bottom of substrate 10 is
another plurality of conductive traces 26 which is used to route the
plurality of conductive vias 20 to corresponding conductive ball receiving
areas 28. As in FIG. 1, which illustrates that each conductive trace 14
has its own associated conductive via and conductive castellation, each
conductive trace 26 on the bottom of substrate 10 has its own associated
via and conductive castellation. Accordingly, there is an association
between each conductive trace on the bottom of the substrate and each
conductive trace on the top of the substrate. This relationship, which
happens to be a one-to-one or exclusive relationship as illustrated, is
what enables semiconductor die 12 to be electrically accessed through
conductive balls which are eventually attached to conductive ball
receiving areas 28 on the bottom of the substrate.
As indicated in FIG. 3, conductive ball receiving areas 28 are arranged in
an array configuration rather than being located along peripheral portions
of substrate 10. The array configuration of the conductive ball receiving
areas is what enables the footprint, or area, of a final BGA semiconductor
device to be reduced in comparison to conventional peripherally leaded
packages. In essence, the conductive traces on the top of the substrate
are used to "fan-out" the connections at the die to the plurality of the
vias, while the conductive traces on the bottom of the substrate are used
to "fan-in" the plurality of conductive vias to the array of conductive
bails. Although as illustrated the conductive ball receiving areas 28 are
pear-shapes, such is not a requirement for practicing the present
invention. Round receiving areas are suitable as well.
A magnified view of a portion of the bottom of substrate 10 is illustrated
in FIG. 4. As FIG. 4, demonstrates, each of the four traces illustrated
has its own conductive castellation, and its own conductive via associated
therewith. For instance, conductive trace 26' a conductive castellation
18' and a conductive via 20' associated therewith, and conductive trace
26" has a conductive castellation 18" and a conductive via 20" associated
therewith.
FIG. 5 is a cross-sectional illustration of a portion of a fully assembled
BGA semiconductor device 30 in accordance with an embodiment of the
present invention. Device 30 includes substrate 10 as excised or
singulated from a larger sheet or strip containing multiple device sites.
As illustrated the substrate includes a conductive trace 14, a bonding
finger 16, a conductive castellation 18, a conductive via 20, a conductive
trace 26, and conductive ball receiving areas 28 as previously described.
Also illustrated in FIG. 5 is an adhesive die attach material 32 which is
used to attach semiconductor die 12 to a surface of substrate 10. Also
included in device 30 is an encapsulation material 34 which in a preferred
form is a plastic resin encapsulant when using an organic substrate. Other
encapsulation means, for example a lid, can instead be used to protect
semiconductor die 12. In its finished form, semiconductor device 30 also
includes a plurality of conductive balls 36 which when using an organic
substrate are preferably solder bails having a composition of tin and lead
at or near eutectic solder, with or without slight alloying with another
metal such as silver.
The cross-sectional view of FIG. 5 is taken through the largest lateral
dimension of semiconductor device 30 and of substrate 10, thus conductive
castellation 18 is really hidden in the view of FIG. 5. Thus, the
castellation is represented by dotted line 37. FIG. 6 is a magnified
cross-sectional view of the peripheral portion of substrate 10 taken
through a conductive castellation 18. In other words, the cross-section is
taken through the smallest lateral dimension of the substrate. Thus the
portion of conductive castellation 18 illustrated in FIG. 6 is the
farthest recessed portion relative to the perimeter of the substrate.
Remaining portions of the conductive castellation exist in another plane
and are thus not illustrated in FIG. 6. For further clarity as to the view
which FIG. 6 illustrates, FIG. 4 includes a line 6--6 through a conductive
castellation which is comparable to the view in FIG. 6.
The view of FIG. 6 is intended to show the manner in which vias and
castellations are made conductive in a typical manufacturing process. The
present invention takes advantage of these current manufacturing
techniques to improve testing processes used to test BGA semiconductor
devices. In a typical process for making an organic substrate, the
conductive traces 14 and 26 formed on the top and bottom of the substrate,
respectively, are formed by first laminating a conductive layer 40,
typically copper, on each surface of the bulk insulating material of the
substrate. As mentioned previously, this laminated layer is
lithographically patterned and etched to define the desired conductive
trace pattern. Holes are formed in the substrate by drilling or punching,
but as formed initially are non-conductive. An electroless plating
operation is performed to deposit a thin plating layer on the sidewalls of
the holes or vias, followed by an electrolytic plating process to build-up
the plating layer thickness. The final composite plating layer is
illustrated as a single plating layer 42 in FIG. 6 fo | | |
