Method and system for reduced column redundancy using a dual column select

Claims

What is claimed is:

1. A memory device, comprising:

an array of subarrays of memory cells, each subarray arranged in rows and columns of memory cells and at least one redundant column of memory cells;

a row address circuit coupled to receive a row address signal for selecting a row of memory cells in a selected subarray;

a column address circuit coupled to receive a first select signal and a second select signal, the column address circuit arranged for selecting a first column of memory cells at a first time from the row of memory cells in response to the first logic state of the first select signal and for selecting a second column of memory cells at the first time from the row of memory cells in response to a first logic state of the second select signal; and

a column redundancy circuit for producing a second logic state of the second select signal in response to a predetermined column address, the column redundancy circuit selecting the at least one redundant column of memory cells from the row of memory cells in response to a second logic state of the second select signal, the first column of memory cells producing the first datum at the first time and the redundant column of memory cells producing a redundant datum at the first time.

2. A memory device as in claim 1, wherein the column redundancy circuit further includes:

a plurality of programmable memory elements for storing the predetermined column address, each programmable memory element coupled to receive a respective address bit for selectively producing a true or complement of the address bit; and

a redundant column decode circuit coupled to receive the true or complement of the address bit from each of the plurality of programmable memory elements for producing the second select signal.

3. A memory device as in claim 1, further comprising:

a first and a second amplifier circuit, each amplifier having an input terminal and an output terminal, each amplifier receiving a datum at the respective input terminal and producing an amplified datum at the respective output terminal at a second time;

a first select transistor having a control terminal and a current path, the current path coupled between the first column of memory cells and the first amplifier circuit, the control terminal coupled to receive the first select signal for applying the first datum to the input terminal of the first amplifier;

a second select transistor having a control terminal and a current path, the current path coupled between the second column of memory cells and the second amplifier circuit, the control terminal coupled to receive the second select signal for applying the second datum to the input terminal of the second amplifier in response to the first logic state of the second select signal; and

a third select transistor having a control terminal and a current path, the current path coupled between the at least one redundant column of memory cells and the second amplifier circuit, the control terminal coupled to receive the second select signal for applying the redundant datum to the input terminal of the second amplifier in response to the second logic state of the second select signal.

4. A memory device as in claim 3, further comprising:

a first input/output line coupled between the first select transistor and the first amplifier circuit; and

a second input/output line coupled between the second select transistor and the second amplifier circuit and coupled to the third select transistor.

5. A memory device as in claim 4, further comprising:

a first group of columns of memory cells including the first column of memory cells;

a first group of input/output lines inducting the first input/output line coupled to receive data at the first time from respective columns of memory cells in the first group of columns of memory cells;

a first group of multiplex transistors for selectively applying a datum from the first group of columns of memory cells to the first amplifier in response to an address signal;

a second group of columns of memory cells including the second column of memory cells;

a second group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the second group of columns of memory cells; and

a second group of multiplex transistors for selectively applying a datum from the second group of columns of memory cells to the second amplifier in response to the address signal.

6. A memory device as in claim 5, wherein the at least one redundant column of memory cells further comprises:

a first group of redundant columns of memory cells for applying data to the first group of input/output lines in response to the first select signal; and

a second group of redundant columns of memory cells for applying data to the second group of input/output lines in response to the second select signal.

7. A memory device as in claim 1, further comprising:

a first and a second amplifier circuit, each amplifier having an input terminal and an output terminal, each amplifier receiving a datum at the respective input terminal and producing an amplified datum at the respective output terminal;

a first select transistor having a control terminal and a current path, the current path coupled between the first column of memory cells and the first amplifier circuit, the control terminal coupled to receive the first logic state of the first select signal for applying the first datum to the input terminal of the first amplifier;

a second select transistor having a control terminal and a current path, the current path coupled between the second column of memory cells and the second amplifier circuit, the control terminal coupled to receive the first logic state of the second select signal for applying the second datum to the input terminal of the second amplifier;

a third select transistor having a control terminal and a current path, the current path coupled between the at least one redundant column of memory cells and the first amplifier circuit, the control terminal coupled to receive the second logic state of the first select signal for applying the redundant datum to the input terminal of the first amplifier; and

a fourth select transistor having a control terminal and a current path, the current path coupled between the at least one redundant column of memory cells and the second amplifier circuit, the control terminal coupled to receive the second logic state of the second select signal for applying the redundant datum to the input terminal of the second amplifier.

8. A memory device as in claim 1, further comprising:

a plurality of banks of sense amplifiers, each bank of sense amplifiers interposed between the selected subarray of memory cells and another subarray of memory cells;

a first sense amplifier in a bank of sense amplifiers coupled to the first column of memory cells, the first column of memory cells in the selected subarray of memory cells;

a second sense amplifier in the bank of sense amplifiers coupled to the second column of memory cells, the second column of memory cells in the selected subarray of memory cells; and

a redundant sense amplifier in the bank of sense amplifiers coupled to the at least one redundant column of memory cells, the at least one redundant column of memory cells in the selected subarray of memory cells.

9. A memory device as in claim 8, further comprising:

a third column of memory cells in the another subarray of memory cells, the third column of memory cells coupled to the first sense amplifier in the bank of sense amplifiers;

a fourth column of memory cells in the another subarray of memory cells, the fourth column of memory cells coupled to the second sense amplifier in the bank of sense amplifiers; and

another at least one redundant column of memory cells in the another subarray of memory cells, the another at least one redundant column of memory cells coupled to the redundant sense amplifier in the bank of sense amplifiers.

10. A memory device as in claim 9, further comprising:

a first group of columns of memory cells including the first column of memory cells;

a first group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the first group of columns of memory cells;

a first group of multiplex transistors for selectively applying a datum from the first group of columns of memory cells to the first amplifier in response to an address signal;

a second group of columns of memory cells including the second column of memory cells;

a second group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the second group of columns of memory cells; and

a second group of multiplex transistors for selectively applying a datum from the second group of columns of memory cells to the second amplifier in response to the address signal.

11. A memory device as in claim 10, wherein the at least one redundant column of memory cells of the selected subarray further comprises:

a first group of redundant columns of memory cells for applying data to the first group of input/output lines in response to the first select signal; and

a second group of redundant columns of memory cells for applying data to the second group of input/output lines in response to the second select signal.

12. A dynamic random access memory device, comprising:

an array of subarrays of memory cells, each subarray arranged in rows and columns of memory cells and at least one redundant column of memory cells, each memory cell including an access transistor and a storage capacitor;

a row address circuit coupled to receive a row address signal for selecting a row of memory cells in a selected subarray;

a column address circuit coupled to receive a first select signal and a second select signal, the column address circuit arranged for selecting a first column of memory cells at a first time from the row of memory cells in response to the first logic state of the first select signal and for selecting a second column of memory cells at the first time from the row of memory cells in response to a first logic state of the second select signal; and

a column redundancy circuit for producing a second logic state of the second select signal in response to a predetermined column address, the column redundancy circuit selecting the at least one redundant column of memory cells from the row of memory cells in response to a second logic state of the second select signal, the first column of memory cells producing the first datum at the first time and the redundant column of memory cells producing a redundant datum at the first time.

13. A memory device as in claim 12, wherein the column redundancy circuit further includes:

a plurality of programmable memory elements for storing the predetermined column address, each programmable memory element coupled to receive a respective address bit for selectively producing a true or complement of the address bit; and a redundant column decode circuit coupled to receive the true or complement of the address bit from each of the plurality of programmable memory elements for producing the second select signal.

14. A dynamic random access memory device as in claim 12, further comprising:

a first and a second amplifier circuit, each amplifier having an input terminal and an output terminal, each amplifier receiving a datum at the respective input terminal and producing an amplified datum at the respective output terminal at a second time;

a first select transistor having a control terminal and a current path, the current path coupled between the first column of memory cells and the first amplifier circuit, the control terminal coupled to receive the first select signal for applying the first datum to the input terminal of the first amplifier;

a second select transistor having a control terminal and a current path, the current path coupled between the second column of memory cells and the second amplifier circuit, the control terminal coupled to receive the second select signal for applying the second datum to the input terminal of the second amplifier in response to the first logic state of the second column address signal; and

a third select transistor having a control terminal and a current path, the current path coupled between the at least one redundant column of memory cells and the second amplifier circuit, the control terminal coupled to receive the second select signal for applying the redundant datum to the input terminal of the second amplifier in response to the second logic state of the second select signal.

15. A dynamic random access memory device as in claim 14, further comprising:

a first input/output line coupled between the first select transistor and the first amplifier circuit; and

a second input/output line coupled between the second select transistor and the second amplifier circuit and coupled to the third select transistor.

16. A dynamic random access memory device as in claim 15, further comprising:

a first group of columns of memory cells including the first column of memory cells;

a first group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the first group of columns of memory cells;

a first group of multiplex transistors for selectively applying a datum from the first group of columns of memory cells to the first amplifier in response to an address signal;

a second group of columns of memory cells including the second column of memory cells;

a second group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the second group of columns of memory cells; and

a second group of multiplex transistors for selectively applying a datum from the second group of columns of memory cells to the second amplifier in response to the address signal.

17. A dynamic random access memory device as in claim 16, wherein the at least one redundant column of memory cells further comprises:

a first group of redundant columns of memory cells for applying data to the first group of input/output lines in response to the first select signal; and

a second group of redundant columns of memory cells for applying data to the second group of input/output lines in response to the second select signal.

18. A dynamic random access memory device as in claim 12, further comprising:

a first and a second amplifier circuit, each amplifier having an input terminal and an output terminal, each amplifier receiving a datum at the respective input terminal and producing an amplified datum at the respective output terminal;

a first select transistor having a control terminal and a current path, the current path coupled between the first column of memory cells and the first amplifier circuit, the control terminal coupled to receive the first logic state of the first select signal for applying the first datum to the input terminal of the first amplifier;

a second select transistor having a control terminal and a current path, the current path coupled between the second column of memory cells and the second amplifier circuit, the control terminal coupled to receive the first logic state of the second select signal for applying the second datum to the input terminal of the second amplifier;

a third select transistor having a control terminal and a current path, the current path coupled between the at least one redundant column of memory cells and the first amplifier circuit, the control terminal coupled to receive the second logic state of the first select signal for applying the redundant datum to the input terminal of the first amplifier; and

a fourth select transistor having a control terminal and a current path, the current path coupled between the at least one redundant column of memory cells and the second amplifier circuit, the control terminal coupled to receive the second logic state of the second select signal for applying the redundant datum to the input terminal of the second amplifier.

19. A dynamic random access memory device as in claim 12, further comprising:

a plurality of banks of sense amplifiers, each bank of sense amplifiers interposed between the selected subarray of memory cells and another subarray of memory cells;

a first sense amplifier in a bank of sense amplifiers coupled to the first column of memory cells, the first column of memory cells in the selected subarray of memory cells;

a second sense amplifier in the bank of sense amplifiers coupled to the second column of memory cells, the second column of memory cells in the selected subarray of memory cells; and

a redundant sense amplifier in the bank of sense amplifiers coupled to the at least one redundant column of memory cells, the at least one redundant column of memory cells in the selected subarray of memory cells.

20. A dynamic random access memory device as in claim 19, further comprising:

a third column of memory cells in the another subarray of memory cells, the third column of memory cells coupled to the first sense amplifier in the bank of sense amplifiers;

a fourth column of memory cells in the another subarray of memory cells, the fourth column of memory cells coupled to the second sense amplifier in the bank of sense amplifiers; and

another at least one redundant column of memory cells in the another subarray of memory cells, the another at least one redundant column of memory cells coupled to the redundant sense amplifier in the bank of sense amplifiers.

21. A dynamic random access memory device as in claim 20, further comprising:

a first group of columns of memory cells including the first column of memory cells;

a first group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the first group of columns of memory cells;

a first group of multiplex transistors for selectively applying a datum from the first group of columns of memory cells to the first amplifier in response to an address signal;

a second group of columns of memory cells including the second column of memory cells;

a second group of input/output lines including the first input/output line coupled to receive data at the first time from respective columns of memory cells in the second group of columns of memory cells; and

a second group of multiplex transistors for selectively applying a datum from the second group of columns of memory cells to the second amplifier in response to the address signal.

22. A dynamic random access memory device as in claim 21, wherein the at least one redundant column of memory cells of the selected subarray further comprises:

a first group of redundant columns of memory cells for applying data to the first group of input/output lines in response to the first select signal; and

a second group of redundant columns of memory cells for applying data to the second group of input/output lines in response to the second select signal.

23. A dynamic random access memory device as in claim 22, further comprising:

a first column select line overlying the selected subarray of memory cells and the another subarray of memory cells, the first column select line receiving a first column select signal for coupling the first group of columns of memory cells to the first group of input/output lines;

a second column select line overlying the selected subarray of memory cells and the another subarray of memory cells, the second column select line receiving a second column select signal for coupling the second group of columns of memory cells to the second group of input/output lines; and

a redundant column select line overlying the selected subarray of memory cells and the another subarray of memory cells, the redundant column select line receiving a redundant column select signal for coupling the redundant group of columns of memory cells to one of the first or second groups of input/output lines, the redundant group of columns having a number of columns equal to the number of columns of memory cells in each of the first and second groups of columns of memory cells.

24. A method of replacing normal columns of memory cells with redundant columns of memory cells in a memory array including the steps of:

activating a row of memory cells in a subarray of the memory array;

activating a plurality of groups of columns of memory cells including at least one defective group of columns and at least one redundant group of columns in the subarray, each column including a memory cell in the row of memory cells;

addressing at least two groups of columns from the plurality of groups of columns in response to a column address signal;

producing a column select signal at a first time for connecting a selected group of columns, excluding the defective group of columns, to a respective group of input/output lines;

inhibiting production of a column select signal corresponding to the at least one defective group of columns; and

producing a redundant column select signal at the first time for connecting the at least one redundant group of columns to a group of input/output lines corresponding to the at least one defective group of columns.

25. A method as in claim 24, further including the steps of:

selectively producing a plurality of true or complementary address bits in response to a predetermined address;

inhibiting production of a column select signal corresponding to the plurality of true or complementary address bits; and

producing the second select signal in response to the plurality of true or complementary address bits.

26. A method as in claim 24, further including the step of activating a plurality of sense amplifiers, each corresponding to a respective column of memory cells, thereby activating the plurality of groups of columns.

27. A method as in claim 24, further including the step of applying a datum from the selected group of columns and the at least one redundant group of columns to a plurality of respective middle amplifiers.

28. A method as in claim 27, further including the step of activating the middle amplifiers at a second time for amplifying each respective datum on a data bus.

29. A method as in claim 24, wherein the step of producing a redundant column select signal at the first time includes producing two redundant column select signals at the first time for connecting two respective redundant groups of columns to two groups of input/output lines corresponding to two defective groups of columns.

30. A method as in claim 29, further including the step of inhibiting production of column select signals corresponding to two defective group of columns.

RELATED APPLICATION

This application claims priority under 35 USC .sctn.119(e)(1) to provisional application number 60/020,375, filed Jun. 25, 1996, now abandoned.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to electronic memory devices and, more particularly, to a method and system for providing reduced column redundancy in a memory device array using a dual column select function.

BACKGROUND OF THE INVENTION

A semiconductor device includes a large number of memory cells arranged along rows and columns which are orthogonal to each other. The density of defects generated in such a semiconductor memory device during manufacturing is relatively independent of the integration density of the device, but is dependent on the semiconductor manufacturing technology. The higher the integration density of the device, the greater is the ratio of the number of normal memory cells to that of defective memory cells. This is one of the advantages obtained by increasing the integration density of a semiconductor memory device. Even if the device, however, includes only one defective memory cell therein, the device cannot operate normally, and therefore, the device is abandoned.

In order to be able to operate a semiconductor device despite such a defective memory cell, a semiconductor memory device incorporates a redundant memory cell array in the main memory cells array along the rows and columns. In this device, when a defective memory cell is detected, the redundancy memory cell array is used instead of a row memory cell array or a column memory cell array. In a semiconductor memory device including such a redundancy memory cell array, the manufacturing yield can be improved.

The conventional semiconductor memory device including a redundancy memory array provides a way to compare all or part of the external address with the address information of the location of defective row or column memory arrays. When such a match between the external address and the defective address is made, the redundancy memory array is used in place of the normal main memory array.

The external address, such as the column address information being given from external terminals, is supplied to both the column factors and the column redundancy decoders from the column address buffers. The column factors group the column addresses such that one output signal from each group is at a unique state from all the other signals in that group. The column redundancy decoders are a set of decoders which contain information of the defective columns in the normal memory array. If no match is made between the address from the address buffers and the column redundancy decoders, the column factors fire and select the appropriate normal column memory array. If, however, a match exists between the address from the column address buffers and the defective column information in the column redundancy decoders, a coincident signal generated from the column redundancy decoders prevents the column factors from firing. Instead, the column redundancy decoders also fires a signal to select the redundant column memory array. Even though redundancy methods and organization are well established in the state of the art, several considerations must be made when evaluating high speed memory architectures.

In conventional memory organizations, sense amplifiers are arranged to sense the state of the data stored in the memory cells. A bank of multiple sense amplifiers is arranged in each memory array to sense, amplify and restore the data on an entire selected row. One or more of these sense amplifiers are selected by the active Y-select (i.e. column select) to connect, through a local bus, with a mid-amplifier. The mid-amplifier can transmit the received data to the output amplifiers near the external terminals, or it can overwrite the data in the storage cell(s) through the sense amplifier(s). In this fashion, a read or write cycle, respectively, can be performed.

The sense amplifiers are organized in groups. Each sense amplifier in the group is associated to one, individual local I/O line pair. Multiple sense amplifiers are associated with the same local I/O line, but only one sense amplifier will be selected to connect to a particular local I/O line as determined by which Y-select fires. To improve bandwidth, the number of sense amplifiers which are accessed during a cycle is increased. This means that the number of sense amplifiers connected to a Y-select increases and the number of local I/O lines needed to service the sense amplifiers must also increase. This creates a problem when column redundancy is considered.

Traditional methods for providing column redundancy is to create a duplicate of the sense amplifiers and information cells used in the normal memory array. For example, a single Y-select is connected to eight sense amplifiers which are associated to eight pairs of local I/O lines. If a defective memory location exists, a redundant Y-select is fired while the normal Y-select is prevented from firing. The redundant memory array, as required by the organization, will have eight redundant sense amplifiers organized similarly to the normal sense amplifiers. The redundant column memory array requires an equal silicon area to the normal memory array silicon area for that Y-select.

As the number of sense amplifiers that are controlled by a single Y-select increase, the silicon area required for the redundant area is a substantially larger portion of the silicon area used of the device. To further aggravate the problem, multiple redundant Y-selects are required to adequately improve yield.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method and system for providing reduced column redundancy in a memory device is presented that substantially reduces or eliminates problems associated with previously developed redundancy methods and organizations for semiconductor memory devices.

The present invention, accordingly, provides a semiconductor memory device that includes a plurality of row address input lines that receive a plurality of row address signals from an external source. A plurality of column address input lines receive a plurality of column address signals from the external source. In addition, a plurality of main memory arrays include a plurality of main memory subarrays. The main memory subarrays include a plurality of memory cells configured into a plurality of memory cell rows and a plurality of memory cell columns. A plurality of redundant memory arrays associate with the main memory arrays. The redundant memory arrays include a plurality of redundant rows of memory cells and a plurality of redundant columns of memory cells. Row address circuitry of the present invention associates with the row address input lines for receiving the plurality of row addresses and generating therefrom a plurality of row factors that associate with a specified one of the plurality of memory cell rows. The row address circuitry includes decode circuitry for decoding the row factors and firing an X-select signal. The row address circuitry further includes row redundancy circuitry for receiving a plurality of row addresses for determining if a match occurs between the received row addresses and the redundant decoder information which, when a match occurs, generates therefrom a signal to prevent the row factors from firing a normal X-select and a redundant row factor that associates a specified one of the plurality of redundant rows. The redundant decoder circuitry decodes the redundant row factor to fire a redundant X-select.

Column address circuitry associates with the column address input lines for receiving the plurality of column addresses and generating therefrom a plurality of column factors for associating with a specified two of the plurality of memory cell columns. The column address circuitry includes decode circuitry for decoding the column factors, from which some of the column factors are split to provide an even and an odd column factor, and firing two Y-select signals of which one is an even type and one is an odd type. The column address circuitry further includes column redundancy circuitry for receiving a plurality of column addresses for determining if a match occurs between the received column addresses and the redundant column decoder information which, when a match occurs, generates therefrom a signal to prevent at least one of the odd or even column factors from firing and that associates with a specified one of the plurality of redundant columns. The redundant decoder circuitry decodes the redundant column signal to fire a redundant Y-select of the same odd or even type as the main memory Y-select which has been disabled. As more than one redundant column decoder can be active at a time, one or both of the main memory column Y-selects can be replaced with redundant column Y-selects of the same type. The Y-selects determine which of the plurality of sense amplifiers are connected to local input/output lines to write or read data. The present invention further includes a grouping of the local input/output lines to which the sense amplifiers are associated and arranged so that even Y-selects allow their associated sense amplifiers to connect to the even local input/output lines and the odd-Y selects allow their associated sense amplifiers to connect to odd local input/output lines. This concept is further extended to allow both an even and an odd redundant Y-select to associate with the same redundant sense amplifiers to allow the redundant sense amplifiers to connect to both the even and odd local input/output lines, of which only one even or odd redundant Y-select connected to the the redundant sense amplifiers will ever be operated, but is not predetermined until the stored redundant address information is determined.

A technical advantage of the present invention is the ability to fire two Y-select or column select signals at a time in the same segment of a memory array. This provides the same amount of repairability with a reduced number of sense amplifiers required to the redundant memory portion of a memory array.

Another technical advantage of the present invention is an architecture that provides reduced sense amplifiers as compared with the known single column select architectures. This results in silicon savings to yield a higher chip-per-wafer count. The present invention requires minimal change in the sense amplifier structure between normal and redundant sense amplifiers in order to achieve the technical advantages of a dual redundant column select.

Since the ability to fire two-Y-select signals exists, this improves the ability to store and retrieve information in and out of the memory during a single cycle of operation. This makes possible a faster device because a greater number of sense amplifiers provide information at a time with the architecture of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:

FIG. 1 provides a schematic block diagram of a memory circuit formed according to the present embodiment of the invention;

FIG. 2 depicts the formation of column factors in response to column address inputs, which column factors serve as inputs to the main memory matrix of the present invention;

FIGS. 3 and 4 are truth tables illustrating the generation of the different column factors of FIG. 2;

FIG. 5 provides a logic circuit for generating two buffered column factor inputs to the main memory matrix of the present invention, and a means to disable the column factors using the column redundant quadrant select (CRQS);

FIG. 6 illustrates in detailed block diagram format the main and redundant memory matrix circuitry of the present invention;

FIG. 7 shows in more detail the sense amplifier and memory array with redundant array configuration of the present invention;

FIG. 8 depicts in yet further detail the column redundant quadrant select (CRQS) signal generation circuits and redundant Y-select circuits of the present invention;

FIG. 9 shows a logic circuit diagram for the A3 through A7 inputs for generating the column redundant decode (CRDEC) circuit of FIG. 8;

FIG. 10 provides a logic circuit diagram for the column redundant Y-select (CRY) circuit of FIG. 8;

FIG. 11 provides a logic circuit diagram for one embodiment of the column redundant quadrant specific (CRQS) block of FIG. 8;

FIG. 12 depicts a logic circuit diagram for one embodiment of the column redundant address (CRA) circuit of FIG. 8; and

FIG. 13 provides a logic circuit diagram for one embodiment of the CRQSTRI circuit component of FIG. 11;

FIG. 14 illustrates a column select organization for two groups of local I/O lines;

FIG. 15 shows column select organization for two groups of local I/O lines using a dual redundant column select attached through a passgate to the same sense amplifier; and

FIG. 16 provides a circuit diagram of a sense amplifier arranged for the dual redundant column select architecture of FIG. 15; and

FIG. 17 provides a truth table illustrating the generation of the different row factors.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is shown a block diagram of a semiconductor memory device which is a 4,194,304 (=2 22) bit dynamic MOS RAM (which is an abbreviation for random access memory). The present invention has application to essentially any semiconductor memory device capable of employing its unique architecture, including such well known memory devices as DRAM, SDRAM, VRAMs, SRAMs, EPROMs, and flash EPROMs. The memory device includes sixteen main memory arrays of which only two are shown. The other fourteen are represented by a series of dots located between the arrays. Furthermore, these sixteen arrays are organized into four groups of four arrays to form four quadrants.

The schematic block diagram of FIG. 1 shows memory circuit 10 to include row address signal, RAS.sub.--, which enters buffer 20. Output from buffer 20 goes to row address buffers 22 which receive addresses A0 through A8. Row address buffers 22 latch and invert the row address to generate true row addresses RA0 through RA8 and inverted row addressed RA0 through RA8. Row factors circuit 24 receives row addresses RA0 and RA0 through RA8 and RA8, as does row redundant decoders circuit 26. Row factors circuit 24 generates twenty-two row factors, RF0 through RF21, and groups them so that RF0 through RF3 travel along lines 28, RF4 through RF11 travel along lines 30, RF12 through RF19 travel along lines 32, and RF20 and RF21 travel along lines 34.

Buffered row factors circuit 36 receives row factors RF0 through RF21 from row factors circuit 24 and sends them to the main memory. Memory matrix 38 contains both the main memory and the redundant memory arrays. Only one factor in the group is high in each of the four factor groups. The high factor signal in each of the factor groups is uniquely associated to the provided external row address. Buffered row factors circuit 36 sends the row factors to all four quadrants of the main memory.

TABLE 1, which appears following the FIGUREs, provides the values for the row factors and their logical interpretation by the present invention.

TABLE 1 shows the row address and inverted row address from row factors RF0 through RF21 that were formed into four groups of factors, RF0 through RF3, RF4 through RF11, RF12 through RF19, and RF20 through RF21. Each row decoder attaches only to one factor from each group of row factors. When all of those lines are high, then the connected decoder circuit component fires. But the connections on all of the other decoders are different, so that they will not fire. This is because only one factor in each of the four groups can be high at a single time.

Returning to FIG. 1, column address signal, CAS, goes to the write buffer 44 and buffer circuit 46. Write buffer 44 also receives write enable signal, WE. Write buffer circuit 44 provides input to D.sub.IN buffer 48, as does DQ input 50. D.sub.IN buffer 48 represents the 16 input buffers used for DQ0-15. Main and redundant memory matrix 38 provides output to Q.sub.OUT buffer circuits 54 which, via line 56, provide DQ output at node 58. Q.sub.OUT buffer 54 represents the 16 output buffers used for DQ0-15.

Buffer circuit 46 provides input to column address buffers 60 which also receives addresses A0 through A8. Column address buffers 60 provides column addresses CA3 and CA3 through CA8 and CA8 to column factors circuit 62. Column addresses CA0 and CA0 through CA2 and CA2 go to local I/0 control circuit 64. Local I/O control circuit 64 provides output via line 66 to main and redundant memory matrix 38. Column addresses CA3 and CA3 through CA8 and CA8 also go to column redundant decoder circuit 68, as does pull-up pulse (PUP) signal 40. The waveforms for PUP are shown below FIG. 12. Column redundant decoder circuit 68 provides input via lines 70 to the buffered column factors circuit 72, which receives column factors CF0 through CF3 via line 74. The operation and circuitry is described in more detail through the figures below and their accompanying text. Buffered column factors circuit 72 provides buffered column factors via lines 76 to main and redundant memory matrix 38. Column factors circuit 62 provides column factors CF4 through CF11 via lines 78 to main and redundant memory matrix 38. FIG. 8 and its accompanying text describe in further detail the operation of the column redundant Y-select features of the present embodiment.

Buffered column factors circuit 72 and buffered row factors circuit 36 control turning off the normal column and row factor pathways to permit redundant memory cells to store data. Buffered column factors circuit 72 receives the normal column factors, and CRQS lines 70 determines whether there is a redundancy match to prohibit firing along a normal pathway.

If one of the signals in one group of factors is low, all normal Y-selects will be kept low. For this reason, although there are twelve lines going into and out of column factors circuit 62, eight of them are allowed to pass unaltered. Four of them go through buffered column factors circuit 72, which allows the CRQS lines 70 to turn these normal factors off.

The column logic of the present invention is to fire two Y-selects in every cycle. In FIG. 1, column address buffers circuit 60 latches the column address at the fall of CAS. Column addresses CA3 and CA3 through CA8 and CA8 are latched to be used directly by the Y-select decode circuitry (see FIGS. 2 through 5). CA0 and CA1 are used to select which local I/O lines should be connected to the mid-amplifiers, and CA2 determines which mid-amplifiers should be connected to the data lines which lead to the output buffers (see FIG. 7). All of the external column addresses go through column address buffer circuit 60 to be buffered and inverted to provide the true and inverted column address.

The buffered true and inverted column addresses go to both the column factor generator circuit 62 and column redundancy logic 68. Column factor logic circuit 68 groups the column add