A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.
This application is a divisional of U.S. application Ser. No. 08/307,519 filed Sep. 16, 1994, now abandoned, which was a divisional of U.S. application Ser. No. 07/982,988, filed Nov. 30, 1992, now U.S. Pat. No. 5,377,153.
A semiconductor memory device comprises a plurality of first memory cells each located at an intersection of each of a plurality of word lines and an associated one of a plurality of bit lines and each having one end connected to the associated bit line; a plurality of memory cell blocks each comprising first memory cells; dummy cell blocks, provided among the memory cell blocks, for electrically isolating those memory cell blocks which are located at both ends from each other, each of the dummy cell blocks comprising second memory cells; main bit lines each provided for each of the memory cell blocks and each of the dummy cell blocks and each connected to an associated one of the bit lines; a main-bit-line control section for performing such control as to apply a predetermined voltage to the main bit lines, connect the main bit lines to associated sense amplifiers or set the main bit lines in an open state based on an address signal; virtual ground lines connected to other terminals of the first memory cells and the second memory cells; main virtual ground lines each provided for each of the memory cell blocks and each of the dummy cell blocks and each connected to an associated one of the virtual ground lines; and a main-virtual-ground-line control section for performing such control as to apply a predetermined voltage to the main virtual ground lines or set the main virtual ground lines in an open state based on an address signal.
A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.
A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.
In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.
