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Claims  |
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What is claimed is:
1. A method of packaging an integrated circuit (IC) in a ball grid array
(BGA) package that has improved BGA package thermal and electrical
characteristics, comprising:
forming upper layer BGA package traces including a Vss trace, a Vdd trace,
and a signal trace;
forming lower layer BGA package traces at least a portion of which traces
are in vertical alignment with a corresponding one of said upper layer BGA
package traces;
wherein solder balls may be attached to regions of said lower layer BGA
package traces to solder said BGA package to an underlying system printed
circuit board;
disposing a BGA core material between said upper and lower layer BGA
package traces;
forming vias that include:
a unitarily-constructed Vss via coupling said upper layer BGA Vss trace to
a corresponding lower layer BGA Vss trace;
a unitarily-constructed Vdd via coupling said upper layer BGA Vdd trace to
a corresponding lower layer BGA Vdd trace;
a unitarily-constructed signal via coupling a said upper layer BGA signal
trace to a corresponding lower layer BGA signal trace; and
disposing a BGA Vss plane intermediate said upper and lower layer BGA
package traces and making electrical contact with said Vss vial;
wherein said BGA Vss plane so disposed improves thermal dissipation and
electrical characteristics of said BGA package.
2. The method of claim 1 further including disposing a BGA Vdd plane
intermediate said BGA Vss plane and said lower layer BGA package traces
and making electrical contact with said Vdd via.
3. The method of claim 2, wherein a chosen one of (a) said upper layer BGA
package traces, a portion of said BGA core material and said BGA Vss
plane, and (b) said BGA Vdd plane, a portion of said BGA core material,
and said lower layer BGA package traces is fabricated with doubled-sided
printed circuit board material.
4. The method of claim 1, wherein:
said upper layer BGA package traces include a first Vss trace disposed over
a center region of said package, and a second Vss trace disposed over a
peripheral region of said package;
further including providing a first unitarily-constructed Vss via coupling
said first Vss trace to a corresponding lower layer BGA first Vss trace;
and
providing a second unitarily-constructed Vss via coupling said second Vss
trace to a corresponding lower layer BGA second Vss trace.
5. The method of claim 1, further including fabricating said BGA core
material from a material selected from the group consisting of (a) FR4
epoxy glass, and (b) pre-preg.
6. The method of claim 1, wherein said BGA Vss plane is vertically
spaced-apart from a substrate of said IC a distance less than about 0.03"
(0.8 mm).
7. The method of claim 1 wherein said upper layer BGA package Vss trace
includes a BGA package IC die plane that is solderable to a substrate of
said IC.
8. A method of packaging an integrated circuit (IC) in a three-layer ball
grid array (BGA) package that has improved BGA package thermal and
electrical characteristics, comprising:
providing a first BGA core sandwiched between first and second surfaces
clad with conductive material;
said conductive material on said first surface defining at least a first
BGA package surface Vdd plane, a first BGA package surface signal trace,
and a first BGA package surface Vss plane;
said conductive material on said second surface forming a BGA Vss plane
having at least three via openings defined therethrough;
providing a second BGA core whose first surface contacts said BGA Vss
plane, and whose second surface defines at least a second BGA package
surface Vdd plane a portion of which is in vertical registration with said
first BGA package surface Vdd plane, a second BGA package surface signal
track portion of which is in vertical registration with said first BGA
package surface signal trace, and a second BGA package surface Vss plane a
portion of which is in vertical registration with said first BGA package
surface Vss plane;
providing a unitarily-constructed Vdd via coupling said first BGA package
surface Vdd plane and said second BGA package surface Vdd plane and
passing through a via opening in said BGA Vss plane without contacting
said BGA Vss plane;
providing a unitarily-constructed signal via coupling said first BGA
package surface signal trace and said second BGA package surface signal
trace and passing through an opening in said BGA Vss plane without
contacting said BGA Vss plane; and
providing a unitarily-constructed Vss via coupling said first BGA package
surface Vss plane and said second BGA package surface Vss plane and
passing through an opening in said BGA Vss plane while contacting said BGA
Vss plane;
wherein said IC includes a substrate to be coupled to a chosen one of said
first BGA package surface Vss plane and said second BGA package surface
Vss plane, and wherein said IC further includes a signal pad coupled by a
bond wire to a signal trace on the chosen first or second BGA package
surface to which said substrate is coupled, and wherein said IC further
includes a Vdd pad coupled by a bond wire to a Vdd plane on the chosen
first or second BGA package surface to which said substrate is coupled;
wherein said BGA Vss plane and said BGA Vdd plane so disposed improve
thermal dissipation and electrical characteristics of said BGA package;
providing solder balls to contact traces and planes on the unchosen of said
first or second BGA package surface.
9. The method of claim 8, wherein:
said first BGA package surface Vss plane includes a first Vss trace
disposed over a center region of said package, and a second Vss trace
disposed over a peripheral region of said package;
said second BGA package surface Vss plane includes a first Vss trace
disposed under a center region of said package, and a second Vss trace
disposed under a peripheral region of said package; and further including:
providing a first unitarily-constructed Vss via coupling said first Vss
trace on said first BGA package surface Vss plane to said first Vss trace
on said second BGA package surface Vss plane; and
providing a second unitarily-constructed Vss via coupling said second Vss
trace on said first BGA package surface Vss plane to said second Vss trace
on said second BGA package surface Vss plane.
10. The method of claim 8, wherein said first BGA core sandwiched between
first and second surfaces clad with conductive material comprises a
double-sided printed circuit board.
11. The method of claim 8, wherein said BGA Vss plane is vertically
spaced-apart from said substrate of said IC a distance less than about
0.03" (0.8 mm).
12. The method of claim 8, wherein at least one of said first and second
BGA core includes a material selected from the group consisting of (a) FR4
epoxy glass, and (b) pre-preg.
13. A method of packaging an integrated circuit (IC) in a four-layer ball
grid array ("BGA") package having improved BGA package thermal and
electrical characteristics, comprising:
providing a first BGA core sandwiched between first and second surfaces
clad with conductive material;
said conductive material on said first surface defining at least a first
BGA package surface Vdd plane, a first BGA package surface signal trace,
and a first BGA package surface Vss plane;
said conductive material on said second surface forming a BGA Vss plane
having at least three via openings defined therethrough;
providing a second BGA core sandwiched between first and second surfaces
clad with conductive material;
said conductive material on said first surface defining a BGA Vdd plane and
having at least three via openings defined therethrough;
said conductive material on said second surface defining at least a second
BGA package surface Vdd plane a portion of which is in vertical alignment
with said first BGA package surface Vdd plane, a second BGA package
surface signal trace a portion of which is in vertical alignment with said
first BGA package surface signal trace, and a second BGA package surface
Vss plane a portion of which is in vertical registration with said first
BGA package surface Vss plane;
providing a unitarily-constructed Vdd via coupling said first BGA package
surface Vdd plane, said second BGA package surface Vdd plane, and said BGA
Vdd plane by passing through a via opening therein while contacting said
BGA Vdd plane, said unitarily-constructed Vdd via passing through a via
opening in said BGA Vss plane without contacting said BGA Vss plane;
providing a unitarily-constructed signal via coupling said first BGA
package surface signal trace and said second BGA package surface signal
trace and passing through vertically aligned via openings in said BGA Vss
plane and in said BGA Vdd plane without contacting either said BGA Vss
plane and BGA Vdd plane;
providing a unitarily-constructed Vss via coupling said first BGA package
surface Vss plane, said second BGA package surface Vss plane, and said BGA
Vss plane by passing through a via opening therein while contacting said
BGA Vss plane, said unitarily-constructed Vss via passing through a via
opening in said BGA Vdd plane without contacting said BGA Vdd plane; and
disposing a third BGA core intermediate said BGA Vss plane and said BGA Vdd
plane;
wherein said IC includes a substrate to be coupled to said first BGA
package surface Vss plane, and further includes a signal pad coupled to a
bond wire coupled to said first BGA package signal trace, and further
includes a Vdd pad coupled to a bond wire coupled to said first BGA
package Vdd plane;
wherein said BGA Vss plane and said BGA Vdd plane so disposed improve
thermal dissipation and electrical characteristics of said BGA package;
providing solder balls to contact traces and planes on said second surface
of said second BGA core.
14. The method of claim 13, wherein:
with respect to said first BGA core, said first BGA package surface Vss
plane includes a first Vss trace disposed over a center region of said
package, and a second Vss trace disposed over a peripheral region of said
package;
with respect to said second BGA core, said second BGA package surface Vss
plane includes a first Vss trace disposed under a center region of said
package, and a second Vss trace disposed under a peripheral region of said
package; and further including:
providing a first unitarily-constructed Vss via coupling said first Vss
trace on said first BGA package surface Vss plane of said first BGA core
to said first Vss trace on said second BGA package surface Vss plane of
said second BGA core; and
providing a second unitarily-constructed Vss via coupling said second Vss
trace on said first BGA package surface Vss plane of said first BGA core
to said second Vss trace on said second BGA package surface Vss plane of
said second BGA core.
15. The method of claim 13, wherein at least one of said first BGA core
sandwiched between first and second surfaces clad with conductive
material, and said second BGA core sandwiched between first and second
surfaces clad with conductive material comprise a double-sided printed
circuit board.
16. The method of claim 13, wherein said BGA Vss plane is disposed closer
to said IC than is said BGA Vdd plane.
17. The method of claim 13, wherein said BGA Vss plane is vertically
spaced-apart from said substrate of said IC a distance less than about
0.03" (0.8 mm).
18. The method of claim 13, wherein at least one of said first BGA core,
said second BGA core, and said third BGA core includes a material selected
from the group consisting of (a) FR4 epoxy glass, and (b) pre-preg. |
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Claims |
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Description |
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FIELD OF THE INVENTION
This invention relates to packaging integrated circuits, and more
particularly to improving thermal and electrical characteristics in ball
grid array packaging for high speed integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits ("ICs") are fabricated on a semiconductor substrate
that is mounted within a typically epoxy or ceramic overmold for later
mounting on a printed circuit board ("PCB"). As fabrication techniques
improve, ICs tend to include circuits with increased complexity and
increased number of input and output leads ("pinouts"). Further, as more
transistors are fabricated on an IC die of a given size, dissipating heat
from the IC becomes a greater challenge.
One packaging system for providing an IC with a large number of pinouts in
a relatively small package area is known as the ball grid array ("BGA")
package. FIG. 1 depicts a standard two-layer BGA mounting system, similar
to the so-called OMNI.TM. system promoted by Motorola, Inc. In this
system, a BGA package 2 includes a double-sided copper clad printed
circuit board ("PCB") 4 with conductive and/or thermal vias 6A, 6B, 6C
connecting upper BGA package conductive traces 8A, 8B, 8C to lower BGA
package conductive traces 10A, 10B, 10C. The 8A traces and the 8B traces
may each be donut-shaped, as may the corresponding 10A and 10B traces. The
various vias preferably are identical and may be referred to
interchangeably as conductive or thermal vias.
The BGA package further includes the IC die 12 to be packaged, and a
plurality of meltable solder balls 14A, 14B, 14C in contact with the lower
conductive traces 10A, 10B, 10C. The upper and lower BGA package traces
8A, 8B, 8C, 10A, 10B, 10C are typically formed by etching the copper clad
upper and lower surfaces of BGA PCB 4. An overmold, shown in phantom as
16, encapsulates and thus protects the IC die 12. Overmold 16 could, of
course, be sized to extend over a greater or lesser portion of the upper
surface of BGA package 2 than what is depicted in FIG. 1.
Package 2 will eventually be soldered to a system printed circuit board
("PCB") 18, whose upper surface includes conductive traces 20A, 20B, 20C
that will contact various of the solder balls 14A, 14B, 14C. Thus, while
FIG. 1 shows BGA package 2 and system PCB 18 spaced apart vertically, in
practice the solder balls and the system PCB traces are placed in contact
with one another, whereupon an infrared reflow process melts the solder
balls. Upon melting, the solder balls electrically and mechanically join
various of the BGA package traces 10A, 10B, 10C to various of the system
PCB traces 20A, 20B, 20C. The various solder balls may be arrayed in a
relatively dense matrix, with adjacent balls being spaced-apart
horizontally perhaps 0.050" to 0.060" (1.3 mm to 1.5 mm). As a result, BGA
package 2 can advantageously provide a dense pattern of pinout connections
with IC 12.
Those skilled in the art will appreciate that IC 12 may include various
semiconductor devices such as bipolar or metal-oxide-semiconductor ("MOS")
transistors, as well as effective resistor and capacitor components. These
transistors and components will form one or more circuits that are
typically coupled to an upper power source Vdd, and to a lower power
source Vss (usually ground).
Bonding wires such as 22, 24 make electrical connection from pads formed on
IC 12 (not shown) to a BGA package trace or plane formed by etching the
copper clad on the upper surface of BGA structure 2. Bond wire 22, for
example, connects to a BGA package Vdd upper plane trace 8A that connects
to a conductive via 6A, which connects to a BGA package Vdd lower plane
trace 10A that connects to a solder ball 14A. On the underlying system PCB
18, one or more system PCB traces 20A couple to the Vdd power source that
is connected to the system PCB 18. In similar fashion, one or more bond
wires (not shown) will couple IC 12 to Vss on the system PCB 18.
Similarly, bonding wire 24 is shown coupled to an upper signal BGA package
trace 8B that is connected to vias 6B, to BGA package lower signal trace
10B, and signal solder balls 14B. On system PCB 18, system PCB traces 20B
couple electrical signals to or from IC 12. Other bonding wires will also
be present but are not shown for ease of illustration. Of course, IC 12
will generally be coupled by various bond wires, upper BGA package traces,
vias, lower BGA package traces to various different signal solder balls,
for contact with various system PCB 18 signal traces.
As shown in FIG. 1, the lower substrate surface of IC 12 is connected to a
BGA package IC die Vss plane 8C, that connects through several vias 6C to
a BGA package lower surface Vss plane 10C to which solder balls 14C are
attached. As noted, Vss connections to IC 12 generally are also brought
out through Vss IC pads, bond wires, traces, vias, traces and solder balls
in a manner similar to what is described herein with respect to the
connections for Vdd. The underlying system PCB 18 includes a system PCB
Vss ground plane 20C that electrically connects to such Vss solder balls,
including solder balls 14C.
BGA package 2 is relatively economical to manufacture because PCB 4 may be
a symmetrical and relatively inexpensive generic commodity. By
symmetrical, it is meant that PCB 4 is manufactured with copper clad on
the upper and lower surfaces of a typically epoxy glass core 22, commonly
referred to as FR4 material. (It is from this copper clad that the upper
and lower BGA package traces or planes 8A, 8B, 8C, 10A, 10B, 10C are
formed.) Alternatively, core 22 may be fabricated from an adhesive-like
resin commonly termed pre-preg.
It is important that PCB 4 be sufficiently rigid so that the various solder
balls will register properly for soldering to corresponding system PCB
traces. As a result, the vertical thickness of core 22 in FIG. 1 will
typically be at least 0.02" to 0.03" (0.5 mm to 0.8 mm).
Although the BGA configuration of FIG. 1 has the advantage of being
inexpensive to fabricate, it has several shortcomings. Specifically, BGA 4
does not provide a good signal plane for current surges into or out of IC
12, and does not do a good job of dissipating heat generated by IC 12. The
relatively poor electrical and thermal performance associated with BGA
structure 4 is especially apparent when IC 12 includes high density, high
frequency digital circuitry. Essentially these performance shortcomings
arise because the efficient system Vss and Vdd planes on PCB 18 are too
far away from IC 12 to be truly effective.
Thermally, although the system PCB Vss plane 20C can sink heat dissipated
by IC 12 and down-conducted through vias 6C, the system PCB Vss plane is
just too remote for good dissipation. The prior art configuration of FIG.
1 has a thermal resistance .theta..sub.ja of about 35.degree. C./W, which
means that for an increase of one Watt dissipation, the junction
temperature of the IC die 12 will increase 35.degree. C. As a result, IC
12 may overheat, or require bulky and relatively expensive heat sinking.
Alternatively, IC 12 may have to be operated at a lower equivalent duty
cycle to reduce dissipation, thus sacrificing IC 12 performance because of
the poor thermal characteristics associated with prior art two-layer BGA
packages.
Electrically, the current paths from the system PCB Vdd plane 20A, up into
IC 12, through the system Vss plane 20C, and vice versa, are simply too
long. As will be described, these long path lengths can result in the Vdd
and Vss potentials within IC 12 impermissibly varying in magnitude during
current surges. What occurs is that an effective inductance L exists in
series with the relatively long power supply current paths. Large mutual
inductances may be present that force some transient surge ground current
to return undesirably through IC 12, rather than through the system PCB
planes. This IC 12 transient surge current flow can cause ground bounce
and crosstalk between various circuits Within IC 12. In addition, the
effective inductance L can contribute to an undesirable time delay for
signals propagating through IC 12.
More specifically, an excessively long path between a signal node on the IC
chip and a signal return ground plane increases the effective series
inductance (L) therebetween. In the presence of current spikes through
such path, the voltage at the Vss pad(s) and/or Vdd pad(s) within IC 12
can deviate or "bounce" from their nominal DC voltage.
Consider, for example, the effect of a relatively long current return path
for a high speed CMOS digital circuit fabricated within IC 12. The output
of circuit typically will include a PMOS pull-up and an NMOS pull-down
transistor coupled in series between Vdd and Vss. When outputting a
digital "1", the NMOS transistor is off, and the PMOS transistor is on,
and the circuit sources current from Vdd through the PMOS transistor to an
output load coupled to Vss. When outputting a digital "0", the PMOS
transistor is off, the NM0S transistor is on and sinks current from the
output load.
But when this CMOS circuit changes states from "1" to "0" or vice versa,
for a brief interval the PM0S and NMOS transistors may both be
simultaneously on due to imperfect switching. When both transistors are on
during transitions a rapid change (or "spike") in current (di/dt) through
the circuit can occur. In the presence of series inductance L, current
spiking results in an L di/dt.apprxeq.dV/dt change or "bounce" in the
voltage present at the Vdd and/or Vss pads on IC 12. Ground bounce results
from this dV/dt for Vdd and/or Vss within IC 12.
Such voltage bouncing within IC 12 is especially troublesome at "0" to "1"
transitions because CMOS transistors exhibit less noise immunity margin
for error near "0" voltage states as contrasted to "1" voltage states. For
this reason, it is especially important that a low inductance impedance
Vss path within IC 12 be maintained.
In addition to producing overshoot and undershoot on output voltage
waveforms, ground bounce can degrade digital switching reliability. This
degradation occurs because any variations in Vdd or Vss within IC 12 can
alter CMOS trip points.
Generally, the configuration of FIG. 1 will exhibit an output impedance
between a signal output pad on IC 12 and Vss of about 250 .OMEGA.. A 250
.OMEGA. output impedance is undesirably high for matching to a system PCB
that typically is characterized by an impedance in the 50 .OMEGA. to 75
.OMEGA. range. The resultant impedance mismatch contributes to overshoot
and ringing on signals coupled from the BGA package to the system PCB. The
configuration of FIG. 1 also exhibits an effective series inductance of
perhaps 12 nh to 15 nh, and an equivalent output shunt capacitance at a
signal output pad of about 1.2 pF.
As noted, the series inductance can produce overshoot and ringing in IC 12
signals, especially when a relatively light capacitive load is to be
driven. Further, the series inductance and shunt capacitance associated
with the two-layer BGA package of FIG. 1 can undesirably delay a signal
pasing through IC 12 by several nanoseconds. If IC 12 includes high speed
switching devices (e.g., wherein the operating frequency is greater than
perhaps 30 MHz), a BGA package-imposed time delay of a few nanoseconds may
be unacceptable.
In summary, there is a need for a BGA package having improved thermal and
electrical characteristics, especially for high speed digital ICs. To
reduce ground bounce and enhance IC operating reliability, such BGA
package should exhibit approximately 50 .OMEGA. output impedance and
decreased effective series inductance. Further, it should be possible to
manufacture such a BGA package using generic symmetrical PCB materials.
The present invention discloses such a BGA package.
SUMMARY OF THE PRESENT INVENTION
In a first three-layer embodiment, the present invention provides a BGA
package with a BGA Vss plane disposed between the upper and lower BGA
package traces. Further, this embodiment also provides upper and lower BGA
package Vss traces on the outer periphery of the BGA package, to help
maintain a low impedance between an IC packaged with the three-layer
embodiment, and the BGA Vss plane. This embodiment is three-layered in
that there are traces at the upper surface of the BGA package, there is an
intermediate BGA Vss plane, and there are traces at the lower surface of
the BGA package.
The additional BGA Vss plane preferably is a copper clad surface on a
portion of PCB material from which the BGA package is fabricated.
IC-generated heat is coupled from the BGA package IC die Vss trace through
vias to the BGA Vss plane, through the lower portion of the same vias to
the BGA package Vss trace on the lower surface of BGA package, as well as
to a Vss plane on the underlying system PCB. The BGA Vss plane is closer
to the IC than is the underlying system PCB, and thus performs an IC heat
sinking function by lowering thermal resistance .theta..sub.ja.
The BGA Vss plane also provides a closer Vss plane for sinking current
output by the IC than is provided by the underlying PCB Vss plane. The
presence of this closer Vss plane reduces series inductance to the IC,
reduces ground bounce, at least for IC output signals transitioning from
"1" to "0", and reduces time delay through the IC. While the closer Vss
plane reduces series inductance, closer Vss plane proximity to the IC
slightly increases shunt capacitance as seen by a BGA package upper
surface trace to Vss. However, the slight increase in shunt capacitance
appears beneficial in reducing noise seen by the IC.
A more preferred embodiment of the present invention provides a four-layer
BGA package that is similar to the above-described three-layer embodiment,
except that a BGA Vdd plane is also provided intermediate the BGA Vss
plane and the traces on the lower surface of the BGA package. This
embodiment is preferred because it may be fabricated from two pieces of
symmetrical printed circuit board material, and because it reduces ground
bounce for "0" to "1", as well as for "1" to "0" IC output signal
transitions.
The BGA Vdd plane provides a plane that is relatively closer to the IC than
is the underlying PCB Vdd plane, and reduces series inductance when the IC
source current, as in a "0" to "1" output signal transition. This "0" to
"1" ground bounce improvement is in addition to the "1" to "0" current
sinking improvement afforded by the BGA Vss plane, which also improves
heat sinking.
Because it provides an even number of planes, the four-layer embodiment is
preferred for ease of fabrication. This embodiment may be manufactured
using two pieces of symmetrical double clad PCB material, wherein the clad
on each piece of material provides two planes. As such, this embodiment
provides technical advantages in ease and economy of fabrication over a
three layer embodiment.
Further, when compared to a-prior art two-layer BGA package, a four-layer
embodiment according to the present invention reduces series inductance by
about 50%, reduces the effective output impedance from about 250 .OMEGA.
to about 50 .OMEGA., and increases shunt capacitance to about 1.3 pF. When
compared to a. prior art two-layer BGA package, the four-layer embodiment
reduces time delay through the packaged IC by about 2 ns, and improves
thermal dissipation by about 50%.
Other features and advantages of the invention will appear from the
following description in which the preferred embodiments have been set
forth in detail, in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view of a conventional two-layer ball grid array
configuration for packaging an integrated circuit, according to the prior
art;
FIG. 2 is a sectional view of a three-layer ball grid array configuration
for packaging an integrated circuit, according to the present invention;
FIG. 3 is a sectional view of a four-layer ball grid array configuration
for packaging an integrated circuit, according to the present invention;
FIG. 4 is a computer simulation comparing voltage wave-forms for the
four-layer embodiment of FIG. 3 and the two-layer embodiment for FIG. 1,
for a CMOS buffer integrated circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In a first three-layer embodiment shown in FIG. 2, the present invention
provides a BBA package 50 with a BGA Vss plane 60 disposed between the
upper and lower BGA package traces 8A, 8B, 8C', and 10A, 10B, 10C, 10C'.
Among these BGA package traces, the present invention adds upper and lower
BGA package Vss traces 8C, 10C' on the outer periphery of the BGA package.
This embodiment is three-layered in that there are traces 8A, 8B, 8C, 8C'
at the upper surface of the BGA package, there is an intermediate BGA Vss
plane 60, and there are traces 10A, 10B, 10C, 10C' at the lower surface of
the BGA package.
The embodiment of FIG. 2 improves thermal dissipation performance and
partially improves electrical performance in a BGA package when compared
to the two-layer embodiment of FIG. 1. These improvements result by
providing a BGA Vss plane 60 relatively close to IC die 12, and by
optionally providing outer Vss planes 8C', 10C' (and associated vias 6C'
and outer solder balls 14C'). Outer planes or traces 8C', 10C' may be
donut-shaped, and are coupled together by the BGA Vss plane 60, to which
planes or traces 8C, 10C are also coupled. This coupling is affected by
the vias 6C, 6C' which pass tightly through via-sized openings in plane 60
such that electrical (and thermal) contact results. By contrast, all other
vias (e.g., 6A, 6B) pass through oversized openings in plane 60 that are
sufficiently large as to not make electrical (or thermal) contact with the
Vss plane 60.
As was the case in FIG. 1, an IC die 12 mounted within the BGA package has
its substrate coupled to a BGA package IC die Vss trace or plane 8C on the
upper surface of the BGA package. A plurality of vias 6C, 6C' electrically
and thermally couple the BGA Vss plane 60 to the BGA package IC die Vss
trace 8C, and to the outer periphery traces 8C', 10C' on the upper and
lower BGA package surfaces. Vss solder balls couple the various Vss traces
on the lower BGA package surface to corresponding Vss planes on an
underlying system PCB. As in the prior art, Vdd solder balls couple the
various Vdd and signal traces on the lower BGA package surface to
corresponding traces and planes on the underlying system PCB. Vdd vias 6A
and signal vias 6B also couple respective Vdd and signal traces 8A, 14A
and 8B, 14B.
It is understood that the BGA Vss plane 60 makes electrical contact with
the Vss vias 6C, 6C', but not with the Vdd vias 6A or the signal vias 6B.
Electrical conne | | |
