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BACKGROUND OF THE INVENTION
The present invention relates in general to graphic video display systems,
and, more particularly, to a graphic video display system having graphic
layers with programmable priority and window sizing.
Graphic video display systems have been known in the art for many years.
Such devices are typically employed, for example, within video games,
personal computers, and computer workstations. Some graphic display
systems visually display multiple layers of text and graphic data within
sizable windows. An example of such a graphic display system is the
combination of an IBM PC-compatible computer and the Microsoft WINDOWS
operating system. These prior art systems typically employ a bit-mapped
display buffer at least as large as the number of pixels displayed upon an
associated video monitor. Objects to be displayed, such as overlapping
windows of data, are all written to the common display buffer.
Some prior art graphic display systems support overlapping windows. Within
these systems, varying portions of displayable windows may be displayed at
any given time, depending upon the size, positioning, and degree of
overlap of the various windows. Accordingly, two separate copies of each
window, or other displayable object, are maintained; an entire copy stored
within a non-displayable region of memory, and the portion presently
displayed, stored within a display buffer.
These prior art graphic display systems typically construct a video display
of multiple objects, such as windows, by writing data representing the
contents of each window sequentially to the display buffer. Objects of
lower display priority are written first, and are subsequently
overwritten, or obscured, by overlapping portions of higher display
priority objects.
The present invention overcomes the requirement, within some prior art
systems capable of displaying multiple overlapping objects, of a common
display buffer at least as large as the number of pixels displayed upon
the video monitor. Rather, a display buffer the size of a single
horizontal scan line is employed. As each horizontal scan line is
displayed, the present invention determines the portions of displayable
objects which overlap with the present scan line, and write those portions
to a single-line display buffer, in order of increasing display priority.
In this manner, the requirement and expense of a full-screen display
buffer is avoided.
Accordingly, it is an object of the present invention to provide a graphic
display system having multiple overlapping objects and a single-line
display buffer.
It is another object of the present invention to provide a graphic display
system having graphic layers with sizable, positionable windows.
It is a further object of the present invention to provide a graphic
display system having graphic layers with programmable display priority.
It is yet another object of the present invention to provide a graphic
display system having sprite graphics which may be interspersed with
graphical layers.
These and other objects and features of the present invention will become
apparent in light of the present specification, drawings and claims.
SUMMARY OF THE INVENTION
The present invention comprises a graphic video display system including at
least one graphic layer. Each of the graphic layers includes a
2-dimensional array of displayable elements visually displayable as pixels
upon a video display. The video display comprises a plurality of
horizontal scan lines, including a first horizontal scan line, a last
horizontal scan line, and a current horizontal scan line. The current
horizontal scan line corresponds to a horizontal scan line to be next
displayed.
A first memory means stores a digital representation of the displayable
elements of the graphic layer. A second memory means stores a digital
representation of the current horizontal scan line. Horizontal sequencing
means sequences from the first horizontal scan line to the last horizontal
scan line.
Programmable window means specifies a displayable portion of an associated
graphic layer. The programmable window means includes means for specifying
horizontal boundaries and vertical boundaries of the displayable portion
of the graphic layer.
The graphic video display system further includes means for determining
whether a region defined by the vertical boundaries of the displayable
portion of a graphic layer overlaps with the current horizontal scan line.
The system further includes means for reading a displayable portion of a
graphic layer which overlaps with the current horizontal scan line from
the first memory means, and means for writing a subset of the displayable
portion of a graphic layer which overlaps with the current horizontal scan
line to the second memory means. This subset is a segment which is
positioned between the horizontal boundries.
In addition, the present graphic video display system includes means for
displaying a digital representation of a horizontal scan line upon a
corresponding horizontal scan line of the video display.
Accordingly, only the portion of a graphic layer which is specified as
displayable by the programmable window means is displayed upon the video
display. This portion of the graphic layer is displayed upon the video
display at a position specified by the horizontal and vertical boundaries.
In the preferred embodiment, the graphic video display system includes at
least two graphic layers, and further includes priority resolving means.
The priority resolving means determines, at positions on the video display
where there is an overlap of the displayable portions of at least two
graphic layers, which of the displayable portions of the graphic layers
are to be displayed on the video display.
Associated with the priority resolving means is priority assigning means
for assigning one of a range of priority values to each of the graphic
layers. These priority values may correspond to a value ranging from a
lowest priority value to a highest priority value. Also associated with
the priority resolving means is priority sequencing means. The priority
sequencing means sequences from the lowest priority value to the highest
priority value. In addition, the priority sequencing means has a current
priority value.
Moreover, in the preferred embodiment, the subset of the displayable
portion of a graphic layer which overlaps with the current horizontal scan
line is only written to the second memory means when the current priority
value is equal to the priority value assigned to that graphic layer.
Accordingly, displayable portions of each of the graphic layers which
overlaps with the current horizontal scan line are sequentially written to
the second memory means. This sequential writing of graphic layers occurs
in order of increasing priority value assigned to the graphic layer. Thus,
graphic layers assigned lower priority values are at least partially
obscured by overlapping graphic layers which are assigned higher priority
values.
Also in the preferred embodiment, the present graphic display system
further includes at least one displayable sprite. Each sprite has an
x-coordinate, a y-coordinate, a priority value, and an associated sprite
pattern. The graphic display system further includes means for determining
whether a portion of a sprite overlaps with the current horizontal scan
line, and means for determining whether a sprite has a priority value
which is equal to the current priority value. In addition, means are
provided for writing a subset of the sprite pattern to the second memory
means. This subset corresponds to the portion of a sprite which overlaps
with the current horizontal scan line, and which has a priority value
equal to the current priority value.
As a result, displayable portions of each of the graphic layers and each of
the sprites overlapping the current horizontal scan line are each
sequentially written to the second memory means. This sequential writing
occurs in order of increasing priority value. Accordingly, graphic layers
and sprites having a lower priority value are at least partially obscured
by overlapping graphic layers and sprites which have a higher priority
value. This priority resolution of graphic layers and sprites, along with
the assignment of variable priority values to the graphic layers, allows
the graphic layers and sprites to be interspersed, as perceived upon the
video display.
In the preferred embodiment, the graphic display system further includes
horizontal scrolling means for horizontally scrolling the displayable
elements of a graphic layer within the window, or displayable portion, of
the graphic layer. Vertical scrolling means vertically scroll the
displayable elements of a graphic layer within the window, or displayable
portion, of the graphic layer. In addition, means are provided for varying
the x-coordinate and y-coordinate of a sprite, whereby the sprite may be
visibly perceived to move upon the video display.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 of the drawings is a diagram of a graphical display system employing
the present invention;
FIG. 2 of the drawings is a diagram of the present graphic display system;
FIG. 3 of the drawings is a diagram of the contents of the dynamic random
access memory;
FIG. 4 of the drawings is a diagram of the 6-bit graphic data format;
FIG. 5 of the drawings is a diagram of the 4-bit graphic data format,
showing, in particular, the expansion of 4-bit data to 6-bit data;
FIG. 6 of the drawings is a diagram of the graphic layer control registers
associated with a single graphic layer;
FIG. 7 of the drawings is a depiction of a graphic layer, showing, in
particular, the horizontal and vertical sizing and positioning of the
graphic layer;
FIG. 8 of the drawings is a diagram of the sprite y-table;
FIG. 9 of the drawings is a diagram of the sprite x/name table;
FIG. 10 of the drawings is a diagram of the sprite pattern table and the
sprite color pointers;
FIG. 11 of the drawings is a priority hierarchy diagram, showing, in
particular, the relationship between graphic layer and sprite block
priorities;
FIG. 12 of the drawings is a depiction of a video screen display, showing,
in particular, sprites and graphic layers having priorities as shown in
FIG. 11;
FIG. 13-A of the drawings is a portion of a state diagram of the main
controller;
FIG. 13-B of the drawings is a portion of a state diagram of the main
controller;
FIG. 13-C of the drawings is a portion of a state diagram of the main
controller;
FIG. 13-D of the drawings is a portion of a state diagram of the main
controller;
FIG. 13-E of the drawings is a portion of a state diagram of the main
controller;
FIG. 14 of the drawings is a diagram of the graphic layer controller;
FIG. 15 of the drawings is a diagram of the sprite controller; and
FIG. 16 of the drawings is a diagram of the line buffer controller and
surrounding circuitry.
DETAILED DESCRIPTION OF THE DRAWINGS
While this invention is susceptible of embodiment in many different forms,
there is shown in the drawings and will herein be described in detail, one
specific embodiment, with the understanding that the present disclosure be
considered as an exemplification of the principles of the invention and is
not intended to limit the invention to the embodiment illustrated.
The present graphic video display system, or graphic video controller
supports multiple, overlapping graphic layers and sprites. In particular,
three graphic layers, designated layer GR1A, layer GR1B, and layer GR2,
respectively, and up to 112 individual sprites are supported.
Associated with each graphic layer is a two-dimensional array of pixels, or
displayable elements. For each graphic layer, a separate region of memory
stores a bit-mapped graphical representation of data to be displayed. For
each displayable element within a graphic layer a 4-bit (for layers GR1A
and GR1B) or 6-bit (for layer GR2) value specifies a color to be displayed
at a corresponding pixel location on a video display.
Each graphic layer includes a programmable window. Rather than displaying
the entire contents of a graphic layer, a subset, or window, may be
designated for display. For each graphic layer, a corresponding window is
defined by specifying the locations of horizontal and vertical boundaries,
which, together, form a rectangular region. The area within the
rectangular region is the displayable window portion of the associated
graphic layer.
In addition, graphic data displayed within a window may be horizontally and
vertically scrolled. Scrolling does not cause a window to move, but
instead causes horizontal or vertical movement of the graphic data visibly
perceived on the video display within a particular window.
A line buffer is employed to "build" a picture to be displayed. An image is
generated on the video display by sequentially drawing each of 256
horizontal scan lines. Once a 256 line screen has been completely drawn,
it is immediately redrawn. The visual persistence of the pixels on the
screen are such that, to the human eye, this line-by-line drawing is not
perceived and a stable image is perceived.
Before each horizontal scan line is displayed, its contents is generated by
the present graphic controller. The graphic controller determines whether
a portion of a graphic layer window or sprite overlaps with the current
horizontal scan line. If so, the overlapping portion is placed into a line
buffer, at a location corresponding to the horizontal position designated
for the window or sprite.
Since the present graphic controller supports multiple, positionable
windows and sprites, overlap of these objects may occur. Whenever such
overlap occurs, priority resolution must take place to determine which of
the overlapping portions is to be displayed (i.e., which portion is "on
top") at the regions of overlap.
Within the present graphic controller, priority values are used to resolve
these apparent conflicts of overlapping objects. Each of the graphic
layers has a programmable priority value. Each sprite has a fixed priority
value. Objects which overlap with the current scan line are sequentially
written to the line buffer in order of increasing priority value. As a
result, lower priority objects are obscured by portions of overlapping
higher priority objects. When all objects overlapping the current
horizontal scan line have been written to the line buffer, the contents of
the line buffer is ready to be displayed.
A host processor is interfaced to the present graphic controller. The host
processor fills the memory regions storing graphic layer and sprite data
with desired values so that desired images may be displayed. In addition,
registers within the present graphic controller which control the sizing
and positioning of graphic layers windows, the priority of graphic layers,
the positioning of sprites, and a palette of colors to be displayed, are
all programmable (i.e., individually addressable by the host processor).
Graphic video display controller 50 is shown in FIG. 1 as comprising a main
controller 200, a graphic layer controller 300, a sprite controller 400, a
line buffer controller 500, a DRAM controller 600, and a sync controller
700. Main controller 200 controls the overall operation of graphic
controller 50. The primary function of main controller 200 is to construct
each horizontal scan line within a video display. On any given horizontal
scan line, one or more graphic layers, as well as one or more sprites, may
be present.
For each horizontal scan line, main controller 200 issues commands to
graphic layer controller 300 via command lines 56, instructing graphic
layer controller 300 to place portions of graphic layers overlapping the
current horizontal scan line within a line buffer associated with line
buffer controller 500. Similarly, for each horizontal scan line, main
controller 200 issues commands to sprite controller 400 via command lines
58, instructing sprite controller 400 to write portions of sprites
overlapping the current horizontal scan line to a line buffer.
Main controller 200 transmits commands to DRAM controller 600 via command
lines 58, instructing DRAM controller 600 to retrieve various types of
data, in various data formats, from an associated dynamic random access
memory (DRAM). In particular, DRAM controller 600 accepts commands from
main controller 200 to retrieve displayable elements from each of the
three graphic layers, to retrieve x coordinates, y coordinates, sprite
pattern pointers and sprite pattern data for the 112 possible sprites, and
to retrieve a horizontal line offset value for the current scan line. In
addition, DRAM controller 600 services general requests for memory
accesses from a host processor. DRAM controller 600 is interfaced with a
DRAM via a conventional memory interface 54.
Line buffer controller 500 controls the operation of two associated line
buffers. These two line buffers operate in a "ping-pong" fashion; while
one line buffer is being written to, the other is being scanned as the
current horizontal line of the video display. When one line buffer has
been completely displayed and the other completely written to, the roles
of the two line buffers are reversed by line buffer controller 500. Line
buffer controller 500 further contains window mask circuitry, so that only
the portion of a graphic layer visible within a designated window is
displayed upon the video display.
Sync controller 700 provides overall timing of video-related signals, such
as horizontal synchronization and vertical retrace synchronization.
FIG. 2 illustrates an overall video display system incorporating the
present graphic controller 50. A typical system incorporating graphic
controller 50 includes a host processor, such as CPU 51, which may be a
conventional microprocessor, such as a type 68000 microprocessor
manufactured by Motorola. CPU 51 commands the operation of graphic
controller 50, by loading desired values into the various control
registers which govern the operation of graphic controller 50. CPU 51
communicates with graphic controller 50 via a conventional processor
interface 53. A dynamic random access memory, DRAM 100, is interfaced to
graphic controller 50 via a conventional memory interface 54, and provides
storage for graphic layer and sprite data. DRAM 100 also provides general
purpose memory for CPU 51. The digital video output 55 of graphic
controller 50, in the form of digital data representing the colors of
pixels on a video display, is converted to composite video, such as
conventional NTSC or PAL video format, via video signal generator 52.
A memory map of the contents of DRAM 100 is shown in FIG. 3. DRAM 100
includes sprite pattern table 120, containing bit-mapped data capable of
being displayed as individual sprites on the video display. DRAM 100
further includes horizontal line offset tables 101, 102 and 103 for
graphic layers GR2, GR1A, and GR1B, respectively. Each of these horizontal
line offset tables is 256 bytes in length, with each entry corresponding
to one of the 256 horizontal scan lines on the video display. Each entry
provides a value controlling the horizontal scrolling of graphic data
within the displayable window portion of the associated graphic layer
which overlaps the corresponding horizontal scan line. Sprite Y-table 170
of DRAM 100 contains the Y coordinates of each of the 112 sprites which
may be displayed. Similarly, sprite X/name table 140 of DRAM 100 contains
an X coordinate and a "name" pointer for each of the 112 displayable
sprites. The "name" pointer selects one of 128 16-pixel by 16-pixel
graphic patterns within sprite pattern table 120.
DRAM 100 further includes data space 104 for graphic layer data and for
general purpose memory available to CPU 51. The specific memory addresses
at which each of the three individual graphic layers, GR2, GR1A, and GR1B
are stored within graphic layer data and general purpose memory data space
104 is programmable, and is controlled by start block registers and block
length registers associated with each graphic layer.
The displayable elements, or pixels, of graphic layer GR2 is stored within
DRAM 100 in a 6-bit per pixel data format, as shown in FIG. 4. Eight
pixels are stored within every three consecutive words of layer GR2 within
DRAM 100. Each of these words is 16 bits in length, with each bit
designated D0 (least significant) through D15 (most significant). Each
horizontal scan line is 256 pixels in width. Accordingly, 32 consecutive
groups of three words are required to store each scan line of layer GR2
data. Each group of three consecutive words comprises a word0 106, a word1
107, and a word2 108. Word0 106 contains the four least significant bits,
D3-D0, of the first four pixels, designated pix0, pix1, pix2, and pix3,
respectively. Word2 108 stores the four least significant bits of the
remaining four pixels of the eight pixel group, designated pix4, pix5,
pix6, and pix7. Word1 107 stores the remaining two most significant bits,
D5-D4, of pix0 through pix7.
Pixel data for graphic layers GR1A, GR1B, and for sprite pattern data, are
all stored in a 4-bit per pixel data format, as shown in FIG. 5. Each
consecutive 16-bit word within the portion of DRAM 100 storing graphic
data for layer GR1A, GR1B, or sprite patterns contain four 4-bit values,
designating the selected colors for four contiguous pixels. Accordingly,
64 consecutive words are required to store each 256-pixel scan line of
data for graphic layers GR1A and GR1B. As shown in FIG. 5, each word 110
stores the 4-bit data for a first pixel, designated pix0, a second pixel,
designated pix1, a third pixel, designated pix2, and a fourth pixel,
designated pix3.
All 4-bit pixel data is converted to a 6-bit format prior to being
displayed on a video monitor as a pixel having a particular color. FIG. 5
illustrates the conversion of the pixel designated pix0 from 4-bit to
6-bit format. 4-bit pixel data 113 is divided into two most significant
bits 114 and two least significant bits 115. A decoder 111 decodes the two
most significant bits 114 to create four selection pointers. Depending
upon the value of the bits 114, one of four selection pointers output from
decoder 111 is activated. In the example illustrated within FIG. 5, the
two most significant bits 114 are presumed to have the digital value "01",
activating selection pointer 116. The selection pointers select one of
four 4-bit regions within a 16-bit color pointer 112.
Color pointer 112 is illustrative of the ten color pointers within the
present graphic controller. Each color pointer comprises a 16-bit
register. Graphic layers GR1A and GR1B each have a corresponding color
pointer. In addition, as shown in FIG. 10, there are eight sprite color
pointers, designated SCP0-SCP7, associated with the sprite pattern table.
These sprite color pointers are explained in further detail below.
In the example of FIG. 5, active pointer 116 selects bits 11 through 8 of
color pointer 112, designated D11-D8, which are read from color pointer
112 as 4-bit data 117. This 4-bit data 117 is combined with the two least
significant bits 115 of the original 4-bit data, to create a 6-bit data
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