The invention relates to a device for reducing unwanted frequency components in digital frequency generation, comprising an accumulator device (4, 5) for generating output signals depending on an input code (F) corresponding to a desired frequency, the accumulator device (4, 5) being connected to at least one memory unit (6, 7) which comprises codes corresponding to wave shapes, and further comprising a generator (1) for generating a random code (P) and a digital/analog converter (9) for generating analog wave shapes. The invention is characterized in that it comprises modulation means (2, 3) for generating a first modulated signal (F.sub.r1) constituting the sum of the input code (F) and the random code (P) and for generating a second modulated signal (F.sub.r2) constituting the difference between the input code (F) and the random code (P), and a calculation unit (8) for regenerating a code corresponding to said input code (F). The invention provides a reduction of unwanted frequency components, so-called spurious components.
Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies f.sub.out without requiring a corresponding increase in the rate f.sub.clk at which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency f.sub.clk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step .phi..sub.s. This method comprises the steps of a) with a count capacity C, counting modulo n.phi..sub.s at a reduced clock frequency (1/n)f.sub.clk to thereby generate a primary substream of digital words, b) phase offsetting the primary substream to form n-1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step .phi..sub.s, c) converting the digital words of each of the primary, and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform, and d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency f.sub.clk.
A non-integer fractional divider divides a reference clock signal having period P by a non-integer ratio K. The divider includes multiplexers to receive a plurality N of clock signals wherein each clock signal is equally phase shifted by a P/N delay. Incrementers coupled to the multiplexers select first and second clock signals between the N clock signals. Such that the phase shift delay between the two selected clock signals is representative of the non-integer value of K. The selected clock signals are combined to output a divided clock signal. The enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal.
The present invention is a sling frame member including a tubular rail and at least two channels formed within the tubular rail. Each of the channels is capable of receiving a sling. Also described herein is a furniture assembly having a set of seat sling rails of the present invention, a set of back sling rails of the present invention, and seat and back panels interconnecting the respective sets of sling rails to form a seating unit.
