Method and apparatus for providing two system architectures in a processor

Claims

What is claimed is:

1. A processor comprising:

an instruction set unit means for executing a first and second instruction set; and

a system unit means, coupled to said instruction set unit means, for selectively operating in a plurality of system configurations each supporting a different system architecture, wherein said second instruction set is executable selectively using either one of a first and a second said plurality of system configurations, and wherein said first instruction set is executable using said first of said plurality of system configurations.

2. The processor of claim 1, said instruction set unit means for executing a first instruction, said first instruction for causing said processor to switch from operating in said first of said plurality of system configurations to operating in said second of said plurality of system configurations.

3. The processor of claim 2, said instruction set unit means for executing a second instruction, said second instruction for causing said processor to switch from operating in said second of said plurality of system configurations to operating in said first of said plurality of system configurations.

4. The processor of claim 1 further comprising:

a storage area for storing a system indication for selecting between said plurality of system configurations; and

said instruction set unit means for executing instructions to alter the state of said system indication.

5. The processor of claim 1, wherein:

said first of said plurality of system configurations includes a first memory management circuit for supporting translation of a first set of addresses into a second set of addresses; and

said second of said plurality of system configurations includes a second memory management circuit for supporting translation of a subset of said first set of addresses into subset of said second set of addresses.

6. The processor of claim 5 further comprising:

a segmentation unit, coupled to said system unit means, for supporting translation of a third set of addresses into said subset of said first set of addresses.

7. The processor of claim 1, wherein:

said first of said plurality of system configurations includes a first event handling circuit for supporting selection of one of a first plurality of routines in response to delivery of a corresponding one of a first plurality of events; and

said second of said plurality of system configurations includes a second event handling circuit for supporting selection of one of a second plurality of routines in response to delivery of a corresponding one of a second plurality of events.

8. The processor of claim 7, wherein said first event handling circuit is also for supporting selection of one of said second plurality of routines in response to delivery of a corresponding one of said first plurality of events.

9. The processor of claim 1, wherein:

said first of said plurality of system configurations and said second of said plurality of system configurations share an I/O address space.

10. The processor of claim 1, wherein:

said first of said plurality of system configurations and said second of said plurality of system configurations both utilize a common instruction pointer, a common set of registers, a common interrupt controller, a common set of control registers, and a common timer register.

11. The processor of claim 1, wherein said first instruction set is compatible with an existing x86 based instruction set.

12. The processor of claim 1, wherein said second instruction set is executable in conjunction with said first of said plurality of system configurations.

13. The processor of claim 1, wherein said instruction set unit means is operable in a first and second instruction set configuration for respectively executing said first and second instruction sets; wherein said first instruction set includes a first instruction which causes said processor to switch from utilizing said first instruction set configuration to utilizing said second instruction set configuration; and

said second instruction set includes a second instruction which causes said processor to switch from utilizing said second instruction set configuration to utilizing said first instruction set configuration.

14. A processor comprising:

an instruction set unit to execute a first and second instruction set;

a system unit selectively operable in a plurality of system configurations each providing a different system architecture, said plurality of system configurations including at least a first system configuration and a second system configuration, said first system configuration providing a first system architecture to execute said first instruction set, said second system configuration providing a second system architecture to execute said first and second instruction sets; and

an internal bus coupled to said instruction set unit and said system unit.

15. The processor of claim 14, wherein said instruction set unit is configured to execute a first instruction which causes said system unit to switch from said first system configuration to said second system configuration.

16. The processor of claim 15, wherein said instruction set unit is configured to execute a second instruction which causes said system unit to switch from said second system configuration to said first system configuration.

17. The processor of claim 14 further comprising:

a storage area for storing a system indication for selecting between said plurality of system configurations; and

said instruction set unit supporting the execution of instructions for altering the state of said system indication.

18. The processor of claim 14, said first system configuration including a first memory management circuit supporting translation of a first set of addresses into a second set of addresses; and

said second system configuration including a second memory management circuit supporting translation of a subset of said first set of addresses into subset of said second set of addresses.

19. The processor of claim 18 further comprising:

a segmentation unit, coupled to said internal bus, supporting translation of a third set of addresses into said subset of said first set of addresses.

20. The processor of claim 14, wherein said first system architecture is compatible with an existing x86 based architecture.

21. The processor of claim 14, wherein said first system configuration includes a first event handling circuit supporting selection of one of a first plurality of routines in response to delivery of a corresponding one of a first plurality of events; and

said second system configuration includes a second event handling circuit supporting selection of one of a second plurality of routines in response to delivery of a corresponding one of a second plurality of events.

22. The processor of claim 21, wherein said first event handling circuit also supports selection of one of said second plurality of routines in response to delivery of a corresponding one of said first plurality of events.

23. The processor of claim 14, wherein said first system configuration and said second system configuration share an I/O address space.

24. The processor of claim 14, wherein said first system configuration and said second system configuration both utilize a common instruction pointer, a common set of registers, a common interrupt controller, a common set of control registers, and a common timer register.

25. The processor of claim 14, wherein said first instruction set is compatible with an existing x86 based instruction set.

26. The processor of claim 14, wherein said second system configuration provides said second system architecture to also execute said first instruction set.

27. The processor of claim 14 further comprising:

a storage area for storing an instruction set indication for selecting between a plurality of instruction set configurations, where said instruction set unit provides each of said plurality of instruction set configurations to execute a different instruction set; and

said instruction set unit supporting the execution of instructions for altering the state of said instruction set indication.

28. The processor of claim 14, wherein said instruction set unit provides a plurality of instruction set configuration each for executing a different instruction set, wherein said system unit and said instruction set unit include circuitry for selectively preventing selection of certain instruction set configurations and said second system configuration.

29. The processor of claim 14, wherein:

said processor is operable in a plurality of privilege modes, said plurality of privilege modes including,

a first privilege mode in which a process executing on said processor may not instruct said processor to modify information corresponding to either of said first system architecture and said second system architecture, and

a second privilege mode in which said process executing on said processor may instruct said processor to modify information corresponding to either of said first system architecture and said second system architecture; and

said instruction set unit provides each of a plurality of instruction set configurations to execute a different instruction set, and said first instruction set includes an instruction which causes said processor to switch from utilizing one instruction set configuration to utilizing another instruction set configuration while said processor is operating in said first privilege mode.

30. The processor of claim 14, said first instruction set and said second instruction set perform operations using a binary compatible integer format and a binary compatible floating-point format.

31. The processor of claim 14, wherein:

said instruction set unit provides each of a pluralitv of instruction set configurations to execute a different instruction set;

a first instruction set configuration for executing said first instruction set includes a first register file for storing data;

a second instruction set configuration for executing said second instruction set includes a second register file for storing data; and

said first instruction set includes an instruction which causes said processor to store in said second register file data stored in said first register file.

32. The processor of claim 14, wherein said first instruction set and said second instruction set share a register file for storing data.

33. A computer system comprising:

a processor including,

an instruction set unit to execute a first and second instruction set,

a storage area having stored therein a system indication,

a system unit, coupled to said storage area, selectively operating in one of a plurality of system configurations based on said system indication, a first of said plurality of system configurations supporting a first system architecture for said first instruction set, a second of said plurality of system configurations supporting a second system architecture for said first and second instruction sets, and

an internal bus coupled to said instruction set unit and said system unit; and

a storage device, coupled to said processor, having stored therein an operating system, where the state of said system indication is altered in response to said processor executing said operating system.

34. The computer system of claim 33, wherein said first of said plurality of system configurations includes a first memory management circuit supporting translation of a first set of addresses into a second set of addresses; and

said second of said plurality of system configurations includes a second memory management circuit supporting translation of a subset of said first set of addresses into subset of said second set of addresses.

35. The processor of claim 34 further comprising:

a segmentation unit, coupled to said internal bus, supporting translation of a third set of addresses into said subset of said first set of addresses.

36. The processor of claim 33, wherein said first of said plurality of system configurations includes a first event handling circuit supporting selection of one of a first plurality of routines in response to delivery of a corresponding one of a first plurality of events; and

said second of said plurality of system configurations includes a second event handling circuit supporting selection of one of a second plurality of routines in response to delivery of a corresponding one of a second plurality of events.

37. The processor of claim 36, wherein said first event handling circuit also supports selection of one of said second plurality of routines in response to delivery of a corresponding one of said first plurality of events.

38. The processor of claim 33, wherein

said storage area also has stored therein an instruction set indication;

said instruction set unit, coupled to said storage area, selectively operating in one of a plurality of instruction set configurations based on said instruction set indication, a first of said plurality of instruction set configurations for executing instructions belonging to said first instruction set, a second of said plurality of instruction set configurations for executing instructions belonging to said second instruction set; and

the state of said instruction set indication is altered in response to said processor executing said operating system.

39. A computer system comprising:

a processor including a system unit operable in at least a first system configuration and a second system configuration, said first system configuration for supporting addressing and event handling functions according to a first technique, said second system configuration for supporting addressing and event handling functions according to a second technique which provides for a larger addressing range than said first technique; and

a storage device, coupled to said processor, having stored therein an operating system for use in conjunction with said second system configuration.

40. The computer system of claim 39, wherein said processor further comprises an instruction set unit for executing instructions from at least a first instruction set and a second instruction set, said instruction set unit for executing instructions in said first instruction set in conjunction with either of said first system configuration and said second system configuration, said instruction set unit for executing instructions in said second instruction set in conjunction with at least said second system configuration.

41. A processor comprising:

an instruction set unit; and

a system unit coupled to said instruction set unit and operable in at least two system configurations, a first of said system configurations for converting a first set of addresses into a second set of addresses using a first method, a second of said system configurations for converting a subset of said first set of addresses into a subset of said second set of addresses using a second method, said first of said system configurations also for translating each of a plurality of events into a corresponding one of a first plurality of addresses using a first technique, said second of said system configurations also for translating each of said plurality of events into a corresponding one of a second plurality of addresses using a second technique.

42. The processor of claim 41, said instruction set unit having at least a first selectable instruction set configuration and a second selectable instruction set configuration, said first selectable instruction set configuration for executing instructions belonging to a first instruction set, said second selectable instruction set configuration for executing instructions belonging to a second instruction set.

43. A method comprising the computer implemented steps of:

selecting a first system mode of a processor for operation, said first system mode supporting a memory management scheme and an event handling scheme;

receiving a first instruction belonging to a first instruction set;

generating a control signal in response to executing said first instruction;

switching from operating in said first system mode to operating in a second system mode of said processor in response to said control signal, said second system mode supporting a different memory management scheme and a different event handling scheme than said first system mode; and

executing instructions from said first instruction set and a second instruction set while operating in said second system mode.

44. The method of claim 43, said step of selecting said first system mode includes the step of altering an indication in a control register on said processor to a first state, said processor configuring to operate in said first system mode while said indication is in said first state.

45. The method of claim 44, said step of switching from operating in said first system mode includes the step of altering said indication to a second state, said processor configuring to operate in said second system mode while said indication is in said second state.

46. In a computer system having a processor which executes instructions from at least a first instruction set and a second instruction set and which supports at least a first event handling scheme and a second event handling scheme, a method for servicing an event comprising the steps of:

A) retrieving, in response to delivery of said event, a gate using said first event handling scheme which corresponds to said event;

B) determining whether said gate identifies said event is to be handled using said second event handling scheme;

C) if said gate identifies said event is to be handled by said second event handling scheme, performing the steps of:

C1) selecting a first routine identified by said gate and belonging to said second event handling scheme, and

C2) executing said first routine to service said event; and

D) if said gate does not identify said event is to be handled by said second event handling scheme, executing a second routine identified by said gate and belonging to said first event handling scheme.

47. The method of claim 46, said step of determining whether said gate identifies said event is to be handled using said second event handling scheme includes the step of inspecting an indication in said gate, said indication indicating whether said event is to be handled by said second event handling scheme.

48. A method for providing at least two compatible memory management schemes in a single processor, said method comprising:

storing control bits that cause a system unit to select between a first and a second paging technique;

sending first addresses generated by executing instructions from a first instruction set to a segmentation unit for translation into second addresses; and

sending both said second addresses and third address generated by executing instructions from a second instruction set to said system unit for translation into physical addresses using the selected paging technique.

49. A processor comprising:

an instruction set unit for executing instructions of at least a first and second instruction sets;

a first means for handling events and for translating addresses;

a second means for handling events and for translating addresses; and

a selecting means for causing one of said first means and said second means to be selected, said first means for use when executing instructions from said first instruction set, and said second means for use when executing instructions from both said first and second instruction sets.

50. The processor of claim 49, wherein said instruction set unit is for executing a first instruction for controlling said selecting means.

51. The processor of claim 49, said selecting means further comprising:

a storage area for storing a system indication for selecting between said first means and said second means said instruction set unit for executing instructions to alter the state of said system indication.

52. The processor of claim 49, wherein:

said first means includes a first memory management circuit for translating addresses; and

said second means includes a second memory management circuit for translating addresses.

53. The processor of claim 49, wherein:

said first means includes a first event handling circuit for selecting one of a first plurality of routines in response to delivery of a corresponding one of a first plurality of events; and

said second means includes a second event handling circuit for selecting one of a second plurality of routines in response to delivery of a corresponding one of a second plurality of events.

54. The processor of claim 49, wherein said first instruction set is compatible with an existing x86 based instruction set.

55. The processor of claim 49, wherein said first instruction set includes a first instruction which causes said instruction set unit to prepare to execute instructions of said second instruction set.

56. The processor of claim 49, wherein said selecting means is also for selectively causing said instruction set unit to configure for executing instructions of one of said first instruction set and said second instruction set.

57. A processor comprising:

a instruction set unit to execute instructions from different instruction sets; and

a system unit coupled to said instruction set unit, said system unit including,

a first event handling unit to select handlers to service all events generated while executing the instructions in at least one of said different instruction sets,

a second event handling unit to select handlers to service all events generated while executing the instructions in all said different instruction sets, and

a selecting unit to select one of said first and second event handling units.

58. The processor of claim 57, wherein said system unit further comprises:

a first paging unit to translate all addresses provided by said instruction set unit while executing the instructions in at least one of said different instruction sets,

a second paging unit to translate all addresses provided by said instruction set unit while executing the instructions in all said different instruction sets, and

said selecting unit to select one of said first and second paging units.

59. The processor of claim 58, wherein said instruction set unit includes a segmentation unit.

60. A processor comprising:

a instruction set unit to execute instructions from different instruction sets; and

a system unit coupled to said instruction set unit, said system unit including,

a first paging unit to translate all addresses provided by said instruction set unit while executing the instructions in at least one of said different instruction sets, and

a second paging unit to translate all addresses provided by said instruction set unit while executing the instructions in any of said different instruction sets, and

a selecting unit to select one of said first and second paging units.

61. The processor of claim 60, wherein said system unit further comprises:

a first event handling unit to select handlers to service all events generated while executing the instructions in at least one of said different instruction sets,

a second event handling unit to select handlers to service all events generated while executing the instructions in any of said different instruction sets, and

said selecting unit to select one of said first and second event handling units.

62. The processor of claim 60, wherein said instruction set unit includes a segmentation unit for use when executing only one of said different instruction sets.

63. A method comprising the computer implemented steps of:

setting control bits to place a processor in a selected one of a first and second system configurations, said first and second system configurations using different techniques for at least one of translating addresses and selecting handlers; and

executing instructions on said processor from both a first and second instruction set while said processor is in said selected system configuration.

64. The method of claim 86 wherein said first and second system configurations use different techniques for both translating addresses and selecting handlers.

65. The method of claim 86 further comprising the steps of:

if said selected system configuration is said first system configuration, translating an address required to execute the instructions using hardware on the processor to walk a set of page tables; and

if said selected system configuration is said second system configuration, translating said address required to execute the instructions by call an operating system routine.

66. The method of claim 63 further comprising the steps of:

recognizing events in response to executing the instructions, wherein said selected system configuration is said first system configuration; and

calling a first handler to service events generated as a result of executing instructions form the first instruction set; and

calling different handlers in response to events generated as a result of executing instructions from the second instruction set.

CROSS-REFERENCE TO RELATED APPLICATION

Ser. No. 08/386,931, titled "Method and Apparatus for Transitioning Between Instruction Sets in a Processor," filed Feb. 10, 1995, now U.S. Pat. No. 5,638,525.

BACKGROUND OF THE INVENTION

1. Field of the invention:

The invention relates to the field of electronic data processing devices. More specifically, the invention relates to the operation of processors.

2. Background information:

As computer systems continue to evolve, it is desirable to develop more technologically advanced processors which use new instruction sets and/or new resources for supporting operating system type functions. For example, it has recently become desirable to develop processors which incorporate RISC based instruction sets and/or which utilize larger address spaces. At the same time, it is desirable to remain compatible with the existing base of software (including operating systems) developed for previous processors. The term architecture is used herein to refer to all or part of a computer system, and may include chips, circuits, and system programs.

One prior art architecture which attempted to deal with this limitation is implemented in the VAX-11. The VAX-11 incorporates a new instruction set and extends the PDP-11 architecture from using 16 addressing bits to using 32 addressing bits. The VAX-11 is capable of executing application programs written in either the new VAX-11 instruction set or the PDP-11 instruction set. However, the VAX-11 has several limitations. One such limitation is that the VAX-11 cannot execute an application program written with instructions from both instruction sets because it lacks the ability to share data generated by the different instruction sets. Thus, the VAX-11 does not provide the option of using the new instruction set where justified by performance advantages and using the existing software where justified by development cost considerations. As a result, software developers have the difficult choice of either incurring large development costs to develop an entirely new application program or forgoing the benefits offered by the new instruction set. Another limitation is that the VAX-11 provides one mechanism for supporting operating system type functionality (e.g., only one memory management mechanism and only one event handling mechanism) and can only accept an operating system written in the new VAX-11 instruction set. As a result, previously developed operating systems were not compatible, and an entirely new operating system had to be developed. Further limitations of the VAX-11 include a lack of non-privileged transitions between VAX-11 and PDP-11 instruction set modes, PDP-11 floating-point instructions, privileged execution in the PDP-11 instruction set mode, and input/output accessing in the PDP-11 instruction set mode.

Another prior art architecture which faces this limitation is the Intel.RTM. 386 processor (manufactured by Intel Corporation of Santa Clara, Calif.). The 386 processor expanded the Intel 286 processor (manufactured by Intel Corporation of Santa Clara, Calif.) architecture from 16 bits to 32 bits. However, the 386 processor did not include a new instruction set, but expanded the instruction set used by the 286 processor. In addition, the 386 processor provided only one method of implementing operating system type functions.

Another prior art architecture which faces this limitation is implemented in the MIPS R4000 processor manufactured by MIPS Computer Systems, Inc. of Sunnyvale, Calif. The R4000 processor expanded the R3000 processor to 64 bits. However, the R4000 processor did not include a new instruction set, but just expanded the instruction set used by the R3000 processor. In addition, the R4000 processor provided only one method for providing operating system type functions.

SUMMARY OF THE INVENTION

A processor having two system configurations is provided. The apparatus generally includes an instruction set unit, a system unit, an internal bus, and a bus unit. The instruction set unit, the system unit, and the bus unit are coupled together by the internal bus. The system unit is capable of selectively operating in one of two system configurations. The first system configuration provides a first system architecture, while the second system configuration provides a second system architecture. The bus unit is used for sending and receiving signals from the instruction set unit and the system unit. According to another aspect of the invention, the instruction set unit is capable of selectively operating in one of two instruction set configurations. The first instruction set configuration provides for the execution of instruction belonging to a first instruction set, while the second instruction set configuration provides for the execution of instructions belonging to a second instruction set.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may best be understood by referring to the following description and accompanying drawings which illustrate the invention. In the drawings:

FIG. 1 illustrates a functional block diagram of one embodiment of the invention;

FIG. 2 is a functional block diagram illustrating the different selectable configurations in which a processor may operate according to one embodiment of the invention;

FIG. 3 is a functional block diagram illustrating software for use according to one embodiment of the invention;

FIG. 4a is a functional block diagram illustrating one technique of event handling according to one embodiment of the invention;

FIG. 4b is a functional block diagram illustrating the information stored when using the selectable configuration shown in FIG. 4a according to one embodiment of the invention;

FIG. 5a is a functional block diagram illustrating another technique of event handling according to one embodiment of the invention;

FIG. 5b is a functional block diagram illustrating the information stored when using the selectable configuration shown in FIG. 5a according to one embodiment of the invention;

FIG. 6a is a functional block diagram illustrating one method of memory management according to one embodiment of the invention;

FIG. 6b is a functional block diagram illustrating another method of memory management according to one embodiment of the invention;

FIG. 7 is a functional block diagram of a computer system according to one embodiment of the invention;

FIG. 8 illustrates a functional block diagram of instruction set unit 203 according to one embodiment of the invention; and

FIG. 9 illustrates a functional block diagram of system unit 207 according to one embodiment of the invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. However, it is understood that the invention may be practiced without these specific details. In other instances, wellknown circuits, structures and techniques have not been shown in detail in order not to obscure the invention.

Although a more detailed explanation will be provided below, it is thought worthwhile to first provide a brief overview of the invention. This application describes a method and apparatus for providing a processor which incorporates a new instruction set and advanced resources for providing operating system type support (e.g., event handling, memory management, etc.), while maintaining compatibility with previously developed software. In one embodiment, the processor can selectively operate in one of two instruction set configurations and in one of two system configurations. The first instruction set configuration and system configuration are similar to and compatible with previously developed processors, and thus are compatible with existing software (including operating systems). However, the second system configuration provides a new system architecture which supports different techniques for providing typical operating system type functions. In addition, the second instruction set configuration provides a new instruction set architecture for which new software (including operating systems) can be written. Furthermore, either instruction set configuration can be used in conjunction with either system configuration. As a result, single programs may utilize both instruction sets, and operating systems may use both system architectures.

FIG. 1 shows a functional block diagram illustrating an overview of one embodiment of the invention. FIG. 1 shows an instruction set architecture 110, an instruction set architecture 120, a system architecture 130, and a system architecture 140.

Instruction set architecture 110 is used for executing instructions from a first instruction set, while instruction set architecture 120 is used for executing instructions from a second instruction set. Thus, instruction set architectures 110 and 120 include all necessary software, firmware and hardware to provide for the execution of two instruction sets--one instruction set each. In one embodiment, instruction set architecture 110 is a CISC (complex instruction set computing) type architecture substantially compatible with an existing instruction set for the Intel x86 Microprocessor family. However, in this embodiment, instruction set architecture 120 is an advanced instruction set architecture which supports a new instruction set. Of course, alternative embodiments may implement the instruction set architectures in any combination of CISC, RISC, VLIW, or hybrid type architectures. In addition, alternative embodiments may implement the instruction set architectures to support two new instruction sets (one instruction set each) or to support two existing instruction sets (one instruction set each).

System architecture 130 supports a first technique of performing operating system type functions, including memory management and event handling. In contrast, system architecture 140 supports a second technique of performing operating system type functions, including memory management and event handling. Thus, system architectures 130 and 140 each include all necessary software, firmware, and hardware to provide for typical operating system functionality. In one embodiment, system architecture 130 is compatible with previously developed operating systems (such as MS-DOS and Windows available from Microsoft Corporation of Redmond, Wash.), while system architecture 140 provides advanced resources which new operating systems may utilize.

In addition, FIG. 1 shows that both instruction set architectures 110 and 120 may be used in conjunction with either of system architectures 130 and 140. In this manner, compatibility is maintained with the existing software base (including operating systems) developed for instruction set architecture 110 and system architecture 130, while allowing for the development of new software (including operating systems) which uses the new instruction set architecture 120 and system architecture. As an example, an operating system written in one of the instruction sets and using one of the system architectures can multitask applications written in either of the instruction sets. While one embodiment is described in which both instruction set architectures 110 and 120 may interact with either of system architectures 130 and 140, alternative embodiments may not support all of the interactions described in FIG. 1. For example, alternative embodiments may not support interaction between instruction set architecture 120 and system architecture 130.

One aspect of the invention is that the processor supports multiple system architectures. Thus, the number of instruction sets and/or system architectures supported, as well as the type of instruction sets and system architectures supported, are not critical to this aspect of the invention. What is important to this aspect of the invention is that the processor can switch between the instruction set architectures and system architectures. For example, alternative embodiments may support one instruction set and two system architectures. As another example, alternative embodiments may support three instruction set architectures and two system architectures. Other alternative embodiments may support three instruction set architectures and three system architectures. An embodiment which supports two instruction set architectures and two system architectures is described so as not to obscure the invention.

FIG. 2 shows a functional block diagram illustrating the selectable configurations or modes of a processor according to one embodiment of the invention. FIG. 2 shows a line 200 representing that the processor includes an instruction set unit 203 and a system unit 207. FIG. 2 also shows that instruction set unit 203 selectively operates in either an instruction set configuration 210 or in an instruction set configuration 220. In one embodiment, instruction set configuration 210 includes segmentation unit 215. Segmentation unit 215 allows for compatibility with existing x86 memory management techniques which utilize segmentation. In addition, FIG. 2 shows system unit 207, which selectively operates in either a system configuration 230 or a system configuration 240.

Instruction set unit 203 executes instructions from a first instruction set while instruction set configuration 210 is selected. In one embodiment, this first instruction set is based on the 16/32-bit x86 instruction set used by existing Intel microprocessors. This instruction set operates using what are referred to as effective or logical addresses. Instruction set configuration 210 sends these effective addresses to segmentation unit 215 which translates them into linear addresses. The technique of segmentation is well known in the prior art and is further described in the following reference: Shanley, Tom and Anderson, Don, ISA System Configuration, MindShare, Inc. (1993). Thus, instruction set configuration 210 with segmentation unit 215 provides a first instruction set architecture. Alternative embodiments which support other instruction sets may require other address translation techniques (rather than or in addition to segmentation), or may not require any address translation.

Instruction set unit 203 executes instructions from a second instruction set which is different from the first instruction set, while instruction set configuration 220 is selected. In one embodiment, this second instruction set is a 64-bit instruction set which operates using the same format of address generated by segmentation unit 215 (i.e., linear addresses). Since this 64-bit instruction set uses linear addresses, it can address the entire 64-bit virtual address space and does not require segmentation. In this manner, instruction set configuration 220 provides a second instruction set architecture.

Thus, instruction set unit 203 includes all necessary software, firmware, and hardware to provide for the execution of two instruction sets. In one embodiment, instruction set unit 203 includes at least one prefetch unit, decode unit, and execution unit, as well as a mechanism for switching between the two instruction set configurations (not shown). One embodiment of instruction set unit 203 will be later described with reference to FIG. 8. While one embodiment of instruction set unit 203 has been described in which it is implemented on the processor, alternative embodiments could implement all or part of instruction set unit 203 in hardware residing outside the processor, or in software.

System unit 207 provides a first system architecture while system configuration 230 is selected. This first system architecture supports typical operating system functions according to a first system technique. In one embodiment, system configuration 230 is compatible with existing x86 processors and includes an event handling unit 233 and a paging unit 236. Event handling unit 233 provides for the selection of the appropriate service routine or handler in response to each of a predefined set of events according to a first event handling method or technique. It is worthwhile to note that the term "event" is used herein to refer to any action or occurrence to which a computer system might respond (i.e., hardware interrupts, software interrupts, exceptions, traps, faults, etc.). As will be further described later with reference to FIGS. 5a and 5b, in one embodiment, event handling unit 233 may be implemented in a corresponding fashion to that of previous x86 based Intel microprocessors (i.e., an interrupt descriptor table stored in memory containing pointers to service routines). In one embodiment, paging unit 236 provides for virtual memory by allowing for the translation of the linear addresses generated by both segmentation unit 215 and instruction set configuration 220 into physical addresses according to a first paging method or technique. As will be described later with reference to FIG. 6a, paging unit 236 is implemented in a corresponding fashion to that of previous x86 based Intel microprocessors (i.e., the linear addresses outputted by segmentation unit 215 and instruction set configuration 220 are used by paging unit 236 to identify a page table, a page described in that table, and an offset within that page).

In contrast, system unit 207 provides a second system architecture while system configuration 240 is selected. This second system architecture is different than the first system architecture and supports typical operating system functions according to a second system technique. In one embodiment, system configuration 240 includes an event handling unit 243 and a paging unit 246. Event handling unit 243 provides for the selection of the appropriate service routine or handler in response to an event according to a second event handling method or technique. As will be further described later with reference to FIGS. 6a and 6b, one embodiment of event handling unit 243 is implemented using an event handler region stored in memory. The event handler region is broken down into fixed size sections (also termed as "entries") of 512 bytes, each containing a 64-bit handler (if additional space is needed to store a handler, a jump may be made to another area in memory). One or more events are assigne