In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n.sup.+ type drain region 5, is disposed so as to surround the n.sup.+ -type drain region 5. Further, a p.sup.+ -type contact region 9 disposed adjacent to an n.sup.+ -type source region 8 is formed so as to extend below the n.sup.+ -type source region 8 so that a parasitic transistor formed by the n.sup.+ -type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.

Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined

The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second embodiment the p+ region of the diode overlaps the n+ region turning the diode into a zener diode. The low doping channel region under the dummy polysilicon layer functions as a channel stopper and suppresses the occurrence of the leakage current caused by the zener diode. The adjustment of the channel stopper length and the controllable gate voltage enables the controlling of a zener voltage. When ESD stress is present at the integrated circuit pad the diode, of either type, goes into a controllable voltage level breakdown.

A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p.sup.+ and n.sup.+ doped regions for cathode connection formed within the n-doped well, and spaced-apart p.sup.+ and n.sup.+ doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n.sup.+ doped region and the n-well. The vertical zener junction has a p.sup.+ doped region sandwiched between two n.sup.+ doped regions. The n.sup.+ doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well. The SCR may further include respective field oxides between the anode p.sup.+ and n.sup.+ doped regions, between the anode n.sup.+ doped region and the vertical zener junction, and between the vertical zener junction and the n-doped well. Also provided is an n-doped substrate version of the SCR. The SCR with the vertical zener junction is characterized as having a relatively low breakdown voltage, having improved current handling capability for more reliable and robust operations, and having a breakdown voltage dependent on the doping concentration of the lighter doped p.sup.+ or n.sup.+ doped region of the vertical zener junction.