 |
Claims  |
|
|
What is claimed is:
1. A network data communication apparatus comprising:
a first port coupled to receive an incoming network data packet;
a data packet segmentation unit in communication with said first port for
segmenting said incoming data packet into a plurality of fixed-size data
cells;
a cell bus in communication with said data packet segmentation unit for
conveying said fixed-sized data cells;
a data packet reassembly unit in communication with said cell bus for
receiving said data cells and for reassembling said data cells into a
network data packet;
a second port in communication with said data packet reassembly unit for
transmitting said network data packet from said data communication
apparatus;
a first additional plurality of ports each in communication with said data
packet segmentation unit, said first additional plurality of ports coupled
to receive incoming network data packets from a plurality of network
source addresses;
a second additional plurality of ports each in communication with said data
packet reassembly unit, said second additional plurality of ports coupled
to transmit reassembled data packets to a plurality of network destination
addresses;
a routing control unit in communication with said cell bus for monitoring
data cell traffic on said cell bus and determining an output port(s) for
network data packets, said routing control unit providing destination
control packets for said data packet reassembly unit;
a routing table memory in communication with said routing control unit,
said routing table memory for storing a data table of said network source
addresses and the ports associated with said source addresses;
a control bus in communication with all of said ports of said network data
communication apparatus for receiving port status data cells relating to
activity associated with each of said ports;
a port status counter coupled to said control bus for accumulating said
port status data cells;
an I/O bus;
bus bridging circuitry coupled between said I/O bus and said cell bus for
conveying data traffic therebetween;
a high-speed network controller coupled to said I/O bus; and
a high-speed network interface coupled to said high-speed network
controller for coupling said network data communication apparatus to a
high-speed network.
2. The network data communication apparatus of claim 1 further comprising a
microprocessor in communication with said I/O bus for handling network
management protocols for said network data communication apparatus.
3. A network data communication apparatus comprising:
a first port coupled to receive an incoming network data packet;
a data packet segmentation unit in communication with said first port for
segmenting said incoming data packet into a plurality of fixed-size data
cells, said data packet segmentation unit comprising:
a data packet synchronizer for synchronizing a received data packet to a
clock signal associated with said network data communication apparatus;
a cell header generator coupled to analyze said data packet for generating
cell headers for data cells constituting said data packet, said cell
header generator comprising:
a field classifier for classifying a field type of said data cell;
a byte counter for counting bytes in a data bit stream constituting said
data packet;
a CRC checker operating on said data bit stream; and
a cell header register coupled to said field classifier, byte counter, and
CRC checker for storing cell header bits responsive to each of said
classifier, counter, and checker, respectively, said cell header bits for
generating said cell headers;
a cell payload generator coupled to receive said data packet and divide it
into fixed-size cell payloads for inclusion with said data cells on said
cell bus;
a cell header and cell payload combiner in communication with said header
generator and said payload generator for combining cell headers with cell
payloads to generate data cells for transmission on said cell bus; and
cell transmission circuitry coupled to receive data cells from said
combiner for transmission onto said cell bus;
a cell bus in communication with said data packet segmentation unit for
conveying said fixed-sized data cells;
a data packet reassembly unit in communication with said cell bus for
receiving said data cells and for reassembling said data cells into a
network data packet;
a second port in communication with said data packet reassembly unit for
transmitting said network data packet from said data communication
apparatus;
a first additional plurality of ports each in communication with said data
packet segmentation unit, said first additional plurality of ports coupled
to receive incoming network data packets from a plurality of network
source addresses; and
a second additional plurality of ports each in communication with said data
packet reassembly unit, said second additional plurality of ports coupled
to transmit reassembled data packets to a plurality of network destination
addresses.
4. The network data communication apparatus of claim 3 wherein said cell
payload generator comprises:
a serial-in/parallel-out (SIPO) register for serially receiving sequential
bits of said data packet for outputting fixed-size cell payloads; and
a cell payload register coupled to said SIPO register for receiving and
holding said fixed-size cell payloads.
5. The network data communication apparatus of claim 4 wherein said cell
header and payload combiner comprises:
a cell transmission multiplexer coupled to said cell header register and
said cell payload register for selecting a cell header and its
corresponding cell payload; and
a bus output register coupled to said cell transmission multiplexer for
holding a combined fixed-size data cell prior to transmission on said cell
bus.
6. The network data communication apparatus of claim 5 wherein said cell
transmission circuitry comprises:
a bus access controller for requesting cell bus access and for generating a
transmission enable signal; and
a bus driver coupled to said bus output register and responsive to said
transmission enable signal for conveying said data cell onto said cell
bus.
7. The network data communication apparatus of claim 6 wherein said bus
driver successively conveys first half of the fixed-size data cell then
the rest of the fixed-size data cell onto said cell bus.
8. A network data communication apparatus comprising:
a first port coupled to receive an incoming network data packet;
a data packet segmentation unit in communication with said first port for
segmenting said incoming data packet into a plurality of fixed-size data
cells, said data packet segmentation unit comprising:
a data packet synchronizer for synchronizing a received data packet to a
clock signal associated with said network data communication apparatus;
a cell header generator coupled to analyze said data packet for generating
cell headers for data cells constituting said data packet;
a cell payload generator coupled to receive said data packet and divide it
into fixed-size cell payloads for inclusion with said data cells on said
cell bus;
a cell header and cell payload combiner in communication with said header
generator and said payload generator for combining cell headers with cell
payloads to generate data cells for transmission on said cell bus; and
cell transmission circuitry coupled to receive data cells from said
combiner for transmission onto said cell bus;
a cell bus in communication with said data packet segmentation unit for
conveying said fixed-sized data cells;
a data packet reassembly unit in communication with said cell bus for
receiving said data cells and for reassembling said data cells into a
network data packet, said data packet reassembly unit comprising:
packet assembly linked list control logic for directing the storage of cell
data into a packet buffer memory, which is in communication with said data
packet reassembly unit, for reassembly of said data packet; and
free linked list control logic for assigning blocks of memory in said
packet buffer memory for storage of said data packet,
wherein the first block of memory for a given data packet is for storing
information about the number of ports associated with said packet buffer
memory said data packet is to be transmitted from;
a second port in communication with said data packet reassembly unit for
transmitting said network data packet from said data communication
apparatus;
a first additional plurality of ports each in communication with said data
packet segmentation unit, said first additional plurality of ports coupled
to receive incoming network data packets from a plurality of network
source addresses; and
a second additional plurality of ports each in communication with said data
packet reassembly unit, said second additional plurality of ports coupled
to transmit reassembled data packets to a plurality of network destination
addresses.
9. The network data communication apparatus of claim 8 further comprising
media access control transmission logic in communication with said second
port and said packet reassembly unit for directing transmission of said
data packet from said packet buffer memory to said network, said
transmission logic notifying said free linked list logic upon transmission
of a packet for freeing blocks of memory in said packet buffer memory.
10. The network data communication apparatus of claim 9 wherein said media
access control transmission logic initiates the transmission of a data
packet prior to complete reassembly in accordance with a dynamically
configurable cut-through transmission parameter.
11. A network switch comprising:
a first plurality of ports each for receiving and transmitting network data
packets;
a first packet processing unit in communication with said first plurality
of ports for segmenting data packets received from said first plurality of
ports into fixed-size data cells and for reassembling fixed-size data
cells into data packets for transmission from at least one of said first
plurality of ports;
a first packet buffer memory coupled to said first packet processing unit
for storing data packets as they are reassembled until they can be
transmitted from at least one of said first plurality of ports;
a cell bus coupled to said first packet processing unit for conveying said
data cells;
a second plurality of ports, each for receiving and transmitting network
data packets;
a second packet processing unit coupled between said second plurality of
ports and said cell bus, said second packet processing unit for segmenting
data packets received on one of said second plurality of ports and for
reassembling data packets to be transmitted from at least one of said
second plurality of ports;
a switch packet routing control unit coupled to said cell bus for
propagating control cells to said packet processing units for identifying
which of said first and second plurality of ports said data packet is to
be transmitted from, said routing control unit monitoring data cell
traffic on said cell bus for associating ports with network addresses; and
a routing table memory coupled to said switch packet routing control unit
for maintaining a table of network addresses associated with each of said
first and second plurality of ports;
an I/O bus;
bus bridging circuitry coupled between said I/O bus and said cell bus for
conveying data traffic therebetween;
a high-speed network controller coupled to said I/O bus; and
a high-speed network interface coupled to said high-speed network
controller for coupling said network data communication apparatus to a
high-speed network.
12. The network switch of claim 11 further comprising a microprocessor in
communication with said I/O bus for handling network management protocols
for said network switch.
13. A method of switching data packets in a network comprising the steps
of:
receiving a data packet on a first network port;
segmenting said data packet into a plurality of fixed-size cells, including
the steps of:
synchronizing the receipt of said data packet with an internal clock
signal;
dividing the data packet into fixed-size cell payloads;
generating cell headers in accordance with an associated cell payload; and
combining a cell header with an associated cell payload to constitute a
fixed-size cell;
propagating said fixed-size cells to a packet reassembly unit associated
with a second network port, including the step of transmitting said
fixed-size cells onto a cell bus;
reassembling said fixed-size cells into a reassembled network data packet,
including the steps of:
receiving the fixed-size cells constituting a data packet; and
storing the cells in a packet buffer memory associated with said second
network port in an order that reassembles the data packet, including the
steps of:
allocating blocks of said packet buffer memory as needed for storage of
said data packet;
maintaining a free pool of pointers to free memory blocks available for
allocation in said packet buffer memory; and
tracking the number of output ports a data packet remains to be transmitted
from;
transmitting said reassembled network data packet from said second network
port; and
transmitting said reassembled network data packet from an additional
plurality of network ports.
14. The method according to claim 13 wherein said transmitting said
reassembled network data packet step comprises the steps of:
decrementing a counter value for the number of ports a packet remains to be
transmitted from upon transmission of a data packet from one port; and
freeing blocks of said packet buffer memory associated with a data packet
after said data packet has been transmitted from all its destination
ports.
15. The method according to claim 14 further comprising the steps of:
each port reporting activity information; and
accumulating port activity information at a central location. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communications in computer networks.
More particularly, the present invention relates to local area network
switching techniques utilizing a cell-based architecture.
2. Background
Local area networks, or LANs, have today become an essential tool in
enterprises utilizing computing machinery. Early LAN implementations were
based on a bus architecture in accordance with various protocols, such as
Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), or other protocols. The
bus-based architecture of early LANs utilized a shared bandwidth bus for
coupling each of the nodes to the network. For example, an early Ethernet
network could comprise a plurality of end-stations sharing a total of 10
Mbps (megabits per second) available bandwidth.
To simplify the wiring needs for local area networks and to exploit
existing wiring structures in many office buildings, network designers
implemented devices known as network hubs or concentrators. In the
simplest form, early hubs essentially shrunk the bus to which the network
components connected to the size of a box fitting in a single closet.
Terminals, or end-stations connecting to the network, were generally
capable of connecting to existing building wiring, such as unshielded
twisted pair (UTP) wiring found in many office buildings for connecting to
a centralized hub in the central wiring closet.
The early network hubs designed for use by the various local area network
protocols still implemented a shared-bandwidth architecture. As user
demands have increased, the shared bandwidth architectures of many LANs
existing today have reached their limits. A number of technologies are
being studied for increased bandwidth protocols, but there exists today a
large installed base of LAN equipment and systems compatible with that
equipment which would be advantageously served by a near term increased
bandwidth solution.
One emerging technology that is fast finding widespread use in the
computing industry is the implementation of LAN switches. LAN switches can
be based on existing network protocols such as Ethernet, Token Ring and
FDDI and are thus compatible with existing network systems. Switching
directs network traffic in a very efficient manner. It sends information
directly from the port of origin to only its destination port, not wasting
traffic in broadcasts to every possible destination. Switching increases
network performance, enhances flexibility and eases configuration changes.
In their simplest configuration, LAN switches are fast multiport bridges
operating at the MAC level two of the data link layer level in the OSI
seven layer networking model. Switching technology enables some key
benefits over traditional LAN networks. First, a 10 Mbps (megabits per
second) or 100 Mbps shared media can be changed to 10 Mbps or 100 Mbps of
dedicated bandwidth per connection. Switches enable the connection of
either a shared segment (a workgroup) or a dedicated user to each port.
Further, this can be accomplished without modifying software or hardware
already running on the work stations. This preserves an initial investment
in older network technology and allows a migration path based on familiar,
well-proven technology with little or no impact on the existing network
operating systems.
LAN switches are a recent development and many early devices are targeted
for small workgroups with four to eight nodes to be attached to a given
switch. It is desirable, and therefore and object of the present
invention, to extend the capabilities of a local area network switch to
provide dedicated bandwidth to increased numbers of ports utilizing an
efficient, scaleable architecture.
SUMMARY OF THE INVENTION
From the foregoing, it can be appreciated that switching technology for
local area networks is a critically important emerging technique to handle
the increasing bandwidth demand in existing network implementations. The
present invention is described with respect to an exemplary embodiment of
an Ethernet cell-based switch. It will be clear that the present invention
may be practiced using other protocols than Ethernet and that the
cell-switching techniques may be implemented in devices other than a
network workgroup switch.
The present invention is described in an exemplary embodiment to be
incorporated into an Ethernet workgroup switch. The Exemplary workgroup
switch provides 24 Ethernet ports and one high-speed network interface.
The 24 Ethernet ports are grouped into three sets of eight ports, each set
being associated with a packet processing unit. The packet processing
units are responsible for receiving Ethernet packets, segmenting them into
fixed-size cells and conveying them on a backplane cell bus incorporated
within the work group switch.
Each packet processing unit in the workgroup switch has associated with it
a packet buffer memory. Each packet processing unit monitors traffic on
the cell bus and collects all the cells transmitted thereon for reassembly
into Ethernet packets in the packet buffer memory. The packet buffer
memory is a shared memory to the extent that it relates to the group of
eight ports associated with a single packet processing unit, however the
packet buffer memories are distributed to the extent that there is one
dedicated for each of the packet processing units. Each received Ethernet
packet is reassembled in each packet buffer memory because the destination
port for the received packet may be one or several ports associated with
one or several of the packet processing units.
Also coupled to the cell bus is a switch packet routing controller which
monitors cell traffic on the cell bus. For each packet that is received,
the switch packet routing controller analyzes the packet to determine
which ports, if any, the packet is to be output from. The switch packet
routing controller propagates a control cell on the cell bus directing
each of the packet processing units how to "route" each packet being
assembled thereby. The switch packet routing controller also has
associated therewith a routing table memory which collects information on
received packets for creating a routing table associating each port with
addresses to which it is in communication.
The exemplary Ethernet workgroup switch also includes a high-speed network
interface. This may be used for a high-speed port, such as an ATM port or
other high-speed protocol connection. The high-speed network interface is
coupled to a high-speed internal bus, such as a PCI bus, which is in
communication with the cell bus through a bus bridging controller. The bus
bridging controller also has associated with it a packet buffer memory
that operates in a manner similar to the packet buffer memories associated
with each of the packet processing units.
There is also provided a backplane control bus referred to as a Management
Information Base (MIB) bus which collects port status data count
information.
A memory space model is implemented which provides for the packet buffer
memories to be shared by each of the ports associated with a particular
packet processing unit. Each packet in a given packet buffer memory is
only reassembled once, with fields specifying the number of ports for the
associated packet processing unit to output the packet onto with a counter
mechanism to make sure the packet is maintained until it has been output
on all designated ports. This supports both broadcast and multicast
packets in an efficient manner.
Other aspects of the present invention include an adjustable switching
cut-through latency control feature which can be used to specify how much
of a packet needs to be received and assembled in a packet buffer memory
before it can start to be retransmitted through a port associated with the
memory's packet processing unit.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects, features and advantages of the present invention will be
apparent from the following detailed description in which:
FIG. 1 illustrates a portion of a network architecture incorporating an
exemplary embodiment network switch in accordance with the present
invention.
FIG. 2 illustrates a block diagram of the architecture of the exemplary
network switching apparatus incorporating numerous aspects of the present
invention.
FIG. 3 illustrates a more detailed block diagram of a portion of the
network switching apparatus for segmenting and reassembiling data packets
in association with a backplane cell bus and a shared packet buffer
memory.
FIG. 4 illustrates a more detailed block diagram of the circuitry
responsible for segmenting data packets into fixed-size cells and
propagating them onto the cell bus.
FIG. 5 illustrates the bit assignments for the fixed size data cells in
accordance with the present invention.
FIG. 6 illustrates a timing diagram for accesses to the backplane cell bus
shared by the packet processing units.
FIG. 7 illustrates the circuitry for packet reassembly and transmission,
utilizing a shared packet buffer memory.
FIG. 8 is a graphical diagram of the packet buffer memory organization for
the shared packet buffer memories in accordance with the present
invention.
FIG. 9 is a more detailed diagram of one field in a packet buffer memory
which identifies packet attributes in accordance with one aspect of the
present invention.
FIG. 10 illustrates the bit assignments for cells to be transmitted over a
cell-based control bus for ports exhibiting receive activity.
FIG. 11 illustrates the bit assignments for the format of a control bus
cell for ports exhibiting transmit activity in accordance with the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
Methods and apparatus are disclosed for a network communications device
which implements a cell-based switching architecture. Although the present
invention is described predominantly in terms of an exemplary embodiment
in which an Ethernet workgroup switch utilizes cell-based techniques, the
concepts and methods disclosed herein are broad enough to encompass other
network communications devices where it is desirable to implement
cell-based switching. The present invention is not limited to the Ethernet
embodiment described with respect to the exemplary embodiment, but may in
fact be applied to other network communications protocols. Throughout this
detailed description, numerous specific details are set forth such as
packet protocols and cell sizes, etc., in order to provide a thorough
understanding of the present invention. To one skilled in the art,
however, it will be understood that the present invention may be practiced
without such specific details. In other instances, well-known control
structures and circuit diagrams have not been shown in detail in order not
to obscure the present invention.
In many instances, components implemented within the present invention are
described at an architectural and/or functional level. Those of ordinary
skill in the art will recognize that the architectures described with
respect to the present invention may be implemented utilizing various
technologies such as application specific integrated circuits (ASICs),
programmed logic, or software running on a form of microprocessor or
microcontroller. Those skilled in the art will understand that the present
invention is not limited to any one particular implementation technique
and that once the functionality to be carried out by such components is
described herein, those of ordinary skill in the art will be able to
implement the invention with various technologies without undue
experimentation. An Exemplary Ethernet Workgroup Switch
Referring now to FIG. 1, there is shown a portion of a network system which
incorporates an exemplary embodiment network switching apparatus in
accordance with the present invention. The exemplary network communication
device 100 is an Ethernet workgroup switch designed to be compliant with
10 Mbps (megabit per second) Ethernet, also referred to as standard IEEE
802.3. The exemplary Ethernet switch 100 includes 24 ports 101-124 for
coupling to either individual data terminal equipment (DTE) units such as
DTEs 130 and 132 or to additional network segments, such as the Ethernet
network segment 140, which is itself coupled to three respective DTEs 141,
142 and 143. The Ethernet switch of FIG. 1 in accordance with an
implemented embodiment of the present invention also includes a high-speed
network interface (shown used as high-speed port 150) for providing
communication between the ports 101-124 and a high-speed network, such as
the ATM network 160. The high-speed network interface may be used to
communicate with other high-speed network protocols or used to cascade
together more than one device 100.
By introducing the Ethernet switch 100 into the portion of the illustrated
network, rather than a traditional repeater, greater network efficiency
and speed may be achieved. Many networks are experiencing bandwidth
shortages. There are several reasons for this, including an increase in
traffic due to the shear number of networked users, the amount of data
transported between client/server applications and the inefficient traffic
patterns of some networks. Switching directs network traffic in a very
efficient manner - it sends information directly from the port of origin
to only its destination port. Thus, although the Ethernet switch 100 is
incorporated in a 10 Mbps Ethernet implementation, it is not necessary for
each of the users of the network to share a total of 10 Mbps bandwidth as
would be the case if a repeater were used in place of the Ethernet switch
100. Accordingly, each of the ports 101-124 is provided with a dedicated
bandwidth of 10 Mbps to each of the links such as those respectively shown
as 135, 136 and 137. While it might be suitable for users 141, 142 and 143
to share the bandwidth available on network segment 140, network users 130
and 132 who may be "power users" are able to respectively benefit from a
dedicated 10 Mbps bandwidth.
Referring now to FIG. 2, there is illustrated a block diagram of the
overall architecture of an implemented embodiment of the Ethernet switch
100 implementing various aspects of the present invention. As noted with
respect to FIG. 1, the Ethernet switch 100 comprises 24 Ethernet ports
101-124. In accordance with the illustrated architecture shown in FIG. 2,
it can be seen that the 24 Ethernet ports of the exemplary embodiment
Ethernet switch are divided into three groups of eight ports. Each group
is associated with a single packet processing unit, 200a, 200b or 200c ,
each of which is respectively associated with a shared packet buffer
memory 210a, 210b or 210c. The packet buffer memories 210 are referred to
as shared packet buffer memories, which as will be seen further herein,
refers to the fact that the 8 local ports serviced a by single packet
processing unit 200 are respectively served by a single one of the packet
buffer memories 210.
The packet processing units 200 are each connected through a cell bus 220.
Also coupled to the cell bus 220 is a switch packet routing controller 230
and an associated routing table memory 235. A minimal working Ethernet
switch core could be assembled using at least one of the packet processing
units 200, the switch packet routing controller 230, the cell bus 220, and
the associated memories 210 and 235 for the packet processing unit and
switch routing controller, respectively. The exemplary embodiment Ethernet
switch also incorporates a microprocessor 240 in communication with a I/O
bus (PCI bus) 245 through a PCI chip set 248. The microprocessor 240 is
serviced by local storage memory 249. The microprocessor 240 is provided
for local computing such as network management (SNMP), etc. The PCI bus
245 is coupled to the cell bus 220 through a PCI/cell bus bridging
controller 250, which is associated with its own packet buffer memory 252.
The exemplary Ethernet switch 100 illustrated in FIG. 2 also incorporates a
Management Information Base (MIB) bus 260 designed to carry switch port
MIB information from each of the packet processing units 200 to a switch
port MIB counter 265 for accumulating the appropriate MIB counter
information for the network management agent running on the microprocessor
240. The switch port MIB counter 265 has associated with it a MIB count
memory 268.
As was described with respect to FIG. 1, the Ethernet switch 100 includes a
high-speed interface for communicating with a high-speed network, such as
the ATM network 160 through a high-speed port 150. Thus, the architecture
illustrated in FIG. 2 incorporates a high-speed networking controller 270
for controlling data flow between the switch 100 and the high-speed
network 160. The Ethernet switching controller 270 communicates with the
PCI bus 245 and is associated with a packet buffer memory 275. The
interaction between the high-speed networking controller 270 and the
packet processing units 200 will be described more fully further herein.
Packet Segmentation and Reassembly
Much of the following information relates to circuitry implemented in the
packet processing units 200 for handling data packets and the interaction
of the packet processing units 200 with the cell bus 220.
The switching architecture in accordance with the present invention is a
cell-based architecture. Data packets, such as Ethernet packets, are
received on a local port of one of the packet processing units 200. The
data packets are segmented into fixed-size cells and propagated on the
cell bus 220. The cell bus 220 is coupled to each of the packet processing
units which receive the fixed-size cells from the cell bus for packet
reassembly in an associated packet buffer memory 210. The format for the
fixed-size cells to be transmitted on the cell bus 220 will be described
in detail further herein with respect to FIG. 5, but in accordance with an
implemented body of the present invention, each cell is defined to be 60
bits in length, 12 bits comprising the cell header information and a
48-bit data unit payload from the segmented Ethernet packet.
FIG. 3 illustrates a general block diagram of a packet processing unit 200.
It can be seen at the functional blocks of the packet processing unit 200
can be broken into two distinct operative sections. Block 400, which will
be described in further detail herein with respect to FIG. 4, is
responsible for receiving Ethernet packets from one of the Ethernet ports
associated with the packet processing unit 200 and segmenting the packet
into fixed-size cells for transmission on the cell bus 220.
The other major component of the packet processing unit 200 is the packet
assembly and transmission control logic 700, which will be described in
detail further herein with respect to FIG. 7. The packet assembly and
transmission control logic 700 receives cell traffic from the cell bus
220, which includes both segmented data packets received on either one of
the local Ethernet ports or through the high-speed network interface as
well as control cells propagated by the switch packet routing controller
230. Responsive to information contained in the control packets from the
routing controller 230, the packet assembly and transmission control logic
700 will direct the storage of the cell traffic in an appropriate location
in the buffer memory 210 for reassembly of data packets for retransmission
if they are to be retransmitted from one of the Ethernet ports associated
with the particular packet processing unit 200. The memory space
organization for the packet buffer memory 210 will be described further
herein with respect to FIG. 8.
FIG. 4 illustrates a more detailed block diagram of the packet
receive/segmentation and cell generation logic 400. When a packet is
received from a local port by the packet processing unit 200, the SFD
checker 410 will first search for the SFD field from the Ethernet packet
preamble to locate the data portion of the packet. The SFD field checker
will directs its FIFO controller portion to write the data bit stream into
the FIFO buffer 415 to be synchronized with the packet processing unit
internal operation. When the FIFO 415 is not empty, the Receive Data Path
Controller 420 will direct the FIFO controller 410 to read the data bit
stream out of the FIFO buffer 415, shifting the data into the 48-bit
serial-in/parallel-out (SIPO) register 425.
Concurrent with segmenting the data payload, the CRC checker 430 will start
calculating CRC information from the data bit stream and check whether a
CRC error occurs at the last byte boundary in the bit stream. The byte
counter 435 will count the number of bytes in the bit stream, while the
field classifier 440 will divide the bit stream into cell data and
classify the cell data into one of four data types: destination address,
source address, cell data not ending the packet, and cell data at the end
of the packet. If any receive errors are detected by the CRC checker, the
error will be indicated as error status in the cell header, as well.
When the SIPO register 425 is full, the receive data path controller 420
will direct the cell data register 445 to load data from the SIPO register
425 and will notify the cell bus access controller 450 to generate a cell
bus 220 access request on behalf of the associated local port. Meanwhile,
the receive data path controller 420 will instruct the cell header
register 455 to load information from the CRC checker 430, the byte
counter 435, and the field classifier 440 to generate the appropriate cell
header. If any kind of receive error is detected, such as a runt packet or
FrameTooLong CRC error or alignment error, the cell type will be marked as
a receive error type instead of the type identified by the field
classifier 440.
After the cell bus access controller 450 receives an acknowledgment for
access to the cell bus 220, the cell bus access controller 450 will select
through the cell header multiplexer (MUX) 460 and the cell data MUX 465,
the appropriate cell header and cell data among all the ports that have
requested access to the cell bus 230. The appropriate header and data will
be transferred as a complete cell on to the cell bus 220 in two successive
clock cycles, 30 bits at a time. The transfer to the cell bus is done
through the cell transmission (TX) MUX 468. The bus output register 470
and tri-state output buffer 475 are used to synchronize transmission of
data cells with the cell bus clock. Once the port selection has been made
by the cell bus access controller 450, the corresponding bus request will
be cleared immediately to keep the bus access pipeline running.
Referring now to FIG. 5 there is shown the cell definition for cells to be
transmitted on the cell bus 220. Each cell is defined as a 60-bit data
unit, which is transferred on the cell bus 220 to carry packet data or
packet routing control information to every device connected on the bus.
In accordance with an implemented embodiment of the present invention, it
takes two system clock cycles to send a data cell on the cell bus with
bits 59-30 being sent first and bits 29-0 being sent second. The format
for the cell bit assignments illustrated in FIG. 5 is with respect to an
exemplary embodiment of the present invention. The source chip number
(bits 59-58) combined with the source port number (bits 57-55) specify the
local port from which the packet data carried in the cell is received. For
a packet processing unit, the source chip number is specified by its BCN
configuration and will be either "00", "01", or "10". A setting of "11" is
reserved for the bridging controller 250. The source port number range is
from "000" through "111" to represent in binary the local ports 1 through
8, respectively.
The cell type field (bits 54-52) specifies the type of field contained in
the cell. A setting of "000" specifies the cell contains destination
address information; "001" specifies the cell contains the packet's source
address field; "010" specifies the cell contains embedded data not ending
a packet; "011" specifies the data field ending a packet; "100" specifies
the packet routing control information; "111" indicates that a receiving
error has occurred; and in accordance with the implemented embodiment;
"101" and "110" are reserved cell types.
The packet data byte count field (bit | | |
