A cache controller operable to control a cache comprising cache lines, each being operable to store data words and validity information indicating that all data words within that cache line are valid. The cache controller comprises a linefill mechanism operable to write data words to a cache line, to provide an indication when each of the data words has been written to the cache and to set the validity information when all data words in the cache line have been written; and a data word accessing mechanism, responsive to a request to access a data word during a linefill operation prior to the validity information being set, to determine from the indication provided by the linefill mechanism whether the data word to be accessed has already been written during the linefill operation and, if so, to provide a signal indicating that the data word is accessible.

A data processing system includes a processor core, a cache memory and a cache controller which operate to allow data accesses to a cache line for which a pending cache linefill operation exists to be serviced for those data words within the cache line that are valid at a particular point in time. One or more status bits are provided in association with each cache line indicating whether a line fill is pending for that cache line. The old data may be manipulated up to the point where the first new data is returned. New data items may be read once they have been written into a victim cache line even though the cache linefill is not completed. Stores to the victim cache line may be made via a fill buffer even though the linefill is still pending. The cache memory may include a content addressable memory (CAM) and the cache memory and controller may support a hit under miss operation.

In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.

There is disclosed an architecture capable of accessing data and instructions of an external memory device using store and forward, which has a processor kernel, a cache module, a prefetch module, a switch, and a store and forward controller. The switch is provided for switching a connection from the processor kernel to the cache module or the prefetch module. The store and forward controller detects access between the prefetch module and the memory device, so as to command the switch to switch the connection from the processor kernel to the prefetch module when the prefetch module transfers data by burst transfer, such that data and instructions transferred from the memory device to the prefetch module are also transferred to the processor kernel.

A method of controlling eviction of cache blocks to override eviction of a value which is reserved for a later operation. When a value is loaded into a cache of the processor and is reserved using a lwarx instruction, it sometimes is evicted from the cache due to the need to store other values in the cache set that the value is mapped to. The present invention provides a method of overriding eviction of reserved values by evicting a selected block of the cache which is a block other than the block containing the reserved value. The reserved value is indicated as being reserved by loading a memory address associated with the value into a reservation unit of the cache, and making a reservation flag in the reservation unit active. In two alternative implementations, the eviction mechanism selects a tentative block for eviction and then determines whether the tentative block is the same as the reserved block (and, if so, chooses a different block for the selected block), or preemptively prohibits the reserved block from being chosen as the selected block. The method of the present invention can be implemented with different types of cache replacement controls, e.g., a random mechanism or a least recently used mechanism.