A unified bi-directional LFSR is fabricated from latches having dual (Forward and Reverse) inputs. Each such latch accepts its inputs upon receipt of a clock signal that is respectively associated with the forward or reverse direction. The appropriate collection of XOR gates exists between latch outputs and the inputs associated with a forward clock signal, so as to produce the forward sequence. Likewise, another appropriate collection of XOR gates exists between the latch outputs and the inputs associated with the reverse clock signal. To produce a "reverse" LFSR corresponding to the polynomial that is the reciprocal of the polynomial for the "forward" LFSR, the latches of the reciprocal (reverse direction) LFSR are construed as being numbered in the opposite order. That is, a single set of latches (register) has both a forward linear feedback network and a reverse linear feedback network. Only one of these two feedback networks is used at a time, but they can intermix forward and reverse steps and appear to index back and forth along the native sequence of the LFSR. That is, steps in reverse undo the most recent forward steps, and vice versa. The bi-directional LFSR is also equipped with a way to preset the latches to a preselected initial value, and it is compatible with the production of all zeros. This last feature is obtained by including an extra latch in the register [(n+1)-many latches for a desired n-many bit word] and using it as a valid bit to qualify as correct the remaining latches in the register.
A digital power-up reset circuit is disclosed which provides a pulse of a predetermined width after a period of time after power-up. Because the power-up circuit is digital, it can be easily implemented in an integrated circuit. Moreover, it is relatively invariable to differences in manufacturing processes from device to device, in contrast to conventional analog (e.g., RC time constant based) power-up reset circuits, which have widely varied output pulses from device to device, and which are highly susceptible to variances in output pulse width due to changes in ambient temperature. The digital power-up reset circuit includes a first linear feedback shift register which starts up in an arbitrary state, and a second linear feedback shift register which defines a desired length of an activation of an output reset signal. When the first linear feedback shift register reaches a known state based on a first counter, the second linear feedback shift register is reset and activates a reset pulse until a second counter reaches a second known state.
A sequence generator is configured to be re-initialized to a value selected derived from a candidate group that is derived from a predetermined value. If and when the re-initializing is performed, it is fully performed within about one clock cycle of setting the sequence generator to the predetermined value. The sequence generator is optionally initialized by a local processor to which it is operatively coupled, after which the processor receives one sequence value each cycle.
A static clock pulse generator comprises a plurality of stages, each of which comprises a reset-set flip-flop and a gating circuit. Complementary outputs of the flip-flop control the gating circuit for supplying clock pulses from a clock input to the output of the stage. When the gating circuit is switched off, it holds the output at a default level. The flip-flop has a set input which receives the output from the preceding stage and a reset input which receives the output from the following stage.
A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value. Then, the bit to be shifted into the shift register is compared with the bit to be shifted out of the shift register. The output signal of the sequential logic device is toggled if no match is detected, and maintained if a match is detected. In other embodiments, functions other than an exclusive OR function can be implemented.
Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.
