A method is described for making an array of dynamic random access memory (DRAM) cells having both a trench and a stacked capacitor within each cell. The method involves forming a trench in the silicon substrate at the capacitor node contact area of the DRAM cell, and depositing an N+ doped polysilicon layer to form an N+/P diode capacitor in the trench. Another N+ doped polysilicon layer is deposited and anisotropically etched back over a patterned silicon nitride/silicon oxide layer in the trench areas to form the bottom electrodes of stacked capacitors with vertically extending sidewalls. An interelectrode dielectric layer is formed on the bottom electrodes and top electrodes are formed from a patterned N+ doped polysilicon layer to complete the array DRAM trench/stacked capacitors. The trench diode capacitor electrically connected in parallel with the stacked capacitor increase the cell capacitance. The vertical extensions on the stacked capacitor further increase the capacitance of the DRAM cell.
A compact polarity-insensitive integrated circuit amplifier is described designed to be powered by a miniature low voltage battery of variable polarity. Low current, polarity corrected voltage sources are integrated into functional blocks to supply low current non-bidirectional elements and to provide a constant polarity bias to a substrate of CMOS circuits. Polarity corrected voltage sources are used to provide a polarity sensing function. The invention is embodied in a Class D amplifier which may comprise four n-channel MOSFET transistors arranged in an H-bridge configuration. Additional driver circuitry is described which increases the voltage of the pulse-width modulated input signal to the MOSFET transistors and also performs a pulse trimming function, which reduces parasitic crowbar currents in the amplifier output stage.
A photoresist plasma pretreatment performed prior to a plasma oxide etch. The plasma pretreatment is performed with an argon plasma or a carbon tetrafluoride and trifluoromethane plasma with lower power than in the main etch or is performed with a plasma of difluoromethane or trifluoromethane and carbon monoxide but no argon diluent gas. Thereby, striations on the oxide wall are reduced.
A method for fabricating a DRAM cell with a vertical pass transistor is provided. The method of the invention includes sequentially forming a drain region, a gate structure, a source region, and a capacitor on a semiconductor substrate in a vertical distribution so that an area used by the drain region is the total area used by the DRAM cell on the substrate. In other world, the gate structure, the source region, and the capacitor are formed above the semiconductor substrate without direct contact.
A DRAM memory cell includes a storage capacitor device with two storage capacitors connected in parallel with one another. One of the storage capacitors is a trench capacitor whereas the other one of the storage capacitors is a stacked capacitor.
The present invention provides a method of manufacturing a semiconductor device, comprising the step of selectively grinding or polishing the peripheral portion and the beveled portion of a target substrate including a semiconductor substrate. The grinding or polishing of the target substrate is performed after the dry etching step for forming a trench in the target substrate, or after the depositing step of a copper layer providing a source of contamination of the process apparatus in forming a Cu-buried wiring. By grinding or polishing the peripheral portion and the beveled portion of the target substrate, the uneven portion in the peripheral portion and the beveled portion can be removed and copper is prevented from being exposed to the outside, thereby avoiding the particle generation and contamination of the process apparatus.
