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Claims  |
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What is claimed is:
1. A method of accessing a semiconductor memory device which includes
a memory cell array having a plurality of memory cells arranged in rows and columns;
specification means, to which address signals are input, for selecting at least some of said memory cells in said memory cell array as specified memory cells;
data input/output means for inputting data into the specified memory cells selected by said specification means, and for outputting data read out from the specified memory cells selected by said specification means;
control means for receiving a first control signal for inputting said address signals into said specification means and a second control signal for controlling outputting of data, read out from the memory cell array, from said data input/output
means, and for controlling said specification means and said data input/output means;
delay means for generating delay signals; and
switching means for receiving the delay signals generated by said delay means, and for selecting one of said delay signals to control outputting of said data;
said method comprising:
a first step of asserting said first control signal;
a second step of, after asserting said first control signal, inputting said address signals into said specification means;
a third step of selecting said specified memory cells in said memory cell array using said specification means;
a fourth step of generating a plurality of said delay signals each having a delay time period equivalent to a different number of basic clock cycles of a basic clock signal using said delay means;
a fifth step of receiving said plurality of said delay signals generated using said delay means in said fourth step and selecting a delay signal equivalent to a number of basic clock cycles N of said basic clock signal, N being a positive integer
.gtoreq.2, using said switching means;
a sixth step of asserting said second control signal; and
a seventh step of outputting data stored in said specified memory cells from said data input/output means in synchronism with said basic clock signal N basic clock cycles after said second control signal is asserted and said basic clock signal
transitions.
2. A method of accessing a semiconductor memory device according to claim 1, wherein
said address signals include row address signals and column address signals; and
said first control signal includes a row enable signal for inputting row address signals into said specification means and a column enable signal for inputting said column address signals into said specification means after a row address of said
memory cells is asserted by an input of said row address signals.
3. A method of accessing a semiconductor memory device according to claim 1, wherein
said address signals include at least row address signals; and
said first control signal includes at least a row enable signal for inputting row address signals into said specification means.
4. A method of accessing a semiconductor memory device according to claim 1, wherein
said address signals include at least column address signals; and
said first control signal includes at least a column enable signal for inputting column address signals into said specification means.
5. A method of accessing a semiconductor memory device according to claim 1, wherein
said delay means includes count means for counting a number of cycles of said basic clock signal; and
said count means generates said delay signals in said fourth step, and supplies said delay signals to said switching means in said fifth step.
6. A method of accessing a semiconductor memory device according to claim 5, wherein
said count means includes shift registers for transferring a trigger signal in response to a signal synchronized with said basic clock signal and supplies the trigger signal to said switching means in said fifth step.
7. A method of accessing a semiconductor memory device according to claim 6, wherein
each of said shift registers includes clocked inverters which operate in response to said signal synchronized with said basic clock signal.
8. A method of accessing a semiconductor memory device according to claim 1, wherein
said switching means includes clocked inverters one of which is selected and then becomes active and switches said number N based on an output signal of a selected clocked inverter.
9. A method of accessing a semiconductor memory device according to claim 8, wherein
said switching means further comprises a fuse section having a plurality of fuses;
said fuses are cut before said first step; and
one of said clocked inverters is selected and becomes active in accordance with states of said plurality of fuses.
10. A method of accessing a semiconductor memory device according to claim 8, wherein
said switching means further comprises a fuse section having a plurality of fuses, and a signal creating section which generates signals in accordance with cutting/non-cutting states of said plurality of fuses, and which supplies said signals to
clock input terminals of said clocked inverters to control operation of said clocked inverters;
said fuses are cut before said first step; and
one of said clocked inverters is selected and becomes active in accordance with cutting/non-cutting states of said plurality of fuses.
11. A method of accessing a semiconductor memory device according to claim 10, wherein
said fuse section further comprises a plurality of latch circuits which are coupled to said plurality of fuses, respectively, and which assume states in accordance with said cutting/non-cutting states of said fuses; and
signals which have been latched by said latch circuits are supplied to said signal creating section in said fifth step.
12. A method of accessing a semiconductor memory device according to claim 11, wherein
said signal creating section comprises logical circuits, to which output signals of said latch circuits are supplied and which generate combination signals; and
said combination signals are respectively supplied to input terminals of said clocked inverters, one of said clocked inverters being selected by said combination signals in said fifth step.
13. A method of accessing a semiconductor memory device according to claim 1, wherein said second control signal is a pulse signal and is not asserted after outputting of data from said data input/output means begins in said seventh step.
14. A method of accessing a semiconductor memory device according to claim 1, wherein
in said second step, said address signals are inputted into said specification means in response to a transition of said basic clock signal.
15. A method of accessing a semiconductor memory device according to claim 2, wherein
said row enable signal is used for inputting said row address signals into said specification means in response to a transition of said basic clock signal; and
said column enable signal is used for inputting said column address signals into said specification means in response to a transition of said basic clock signal.
16. A method of accessing a semiconductor memory device according to claim 3, wherein
said row enable signal is used for inputting said row address signals into said specification means in response to a transition of said basic clock signal.
17. A method of accessing a semiconductor memory device according to claim 4, wherein
said column enable signal is used for inputting said column address signals into said specification means in response to a transition of said basic clock signal.
18. A method of accessing a semiconductor memory device including
a memory cell array having a plurality of memory cells arranged in rows and columns;
specification means, to which row address signals and column address signals are input, for selecting at least some of said memory cells in said memory cell array as specified memory cells;
data input/output means for inputting data into the specified memory cells selected by said specification means, and for outputting data read out from the specified memory cells selected by said specification means; and
control means for receiving a first control signal, a second control signal and a third control signal, and for controlling said specification means and said data input/output means,
said first control signal for inputting said row address signals into said specification means,
said second control signal for inputting said column address signals into said specification means,
said third control signal for controlling a beginning of outputting of data, read out from said memory cell array, from said data input/output means;
said method comprising:
a first step of asserting said first control signal;
a second step of inputting said row address signals into said specification means in response to said first control signal;
a third step of selecting a row of said specified memory cells in said memory cell array using said specification means;
a fourth step of asserting said second control signal;
a fifth step of inputting said column address signals in response to said second control signal;
a sixth step of selecting a column of said specified memory cells in said memory cell array using said specification means;
a seventh step of activating said third control signal;
an eighth step of un-activating said third control signal; and
after said eighth step, a ninth step of outputting data stored in said specified memory cells from said data input/output means in synchronism with a basic clock signal N basic clock cycles, N being .gtoreq.2, after said third control signal was
activated and said basic clock signal transitioned.
19. A method of accessing a semiconductor memory device according to claim 18, wherein
said semiconductor memory device further includes delay means for generating delay signals, each of said delay signals having a delay time period equivalent to a different number of cycles of said basic clock signal and switching means for
receiving said delay signals and for selecting one of said delay signals to control said outputting of said data; and
after said sixth step and before said seventh step, the number of said N basic clock cycles is selected.
20. A method of accessing a semiconductor memory device according to claim 19, wherein
said delay means includes count means for counting a number of cycles of said basic clock signal; and
after said sixth step and before said seventh step, said count means generates said delay signals having a delay time period equivalent to the different number of cycles of said basic clock signal.
21. A method of accessing a semiconductor memory device according to claim 20, wherein
said count means includes shift registers for transferring a trigger signal in response to a signal synchronized with said basic clock signal and, after said sixth step and before said seventh step, supplies the trigger signal to said switching
means.
22. A method of accessing a semiconductor memory device according to claim 21, wherein
each of said shift registers includes clocked inverters which operate in response to said signal synchronized with said basic clock signal.
23. A method of accessing a semiconductor memory device according to claim 21, wherein
said switching means receives the delay signals output from said delay means in said sixth step and includes clocked inverters one of which is selected and then becomes active; and
said number N is determined by an output signal of a selected clocked inverter.
24. A method of accessing a semiconductor memory device according to claim 23, wherein
said switching means further comprises a fuse section having a plurality of fuses;
said fuses are cut before said first step; and
one of said clocked inverters is selected and becomes active in accordance with states of said plurality of fuses.
25. A method of accessing a semiconductor memory device according to claim 23, wherein
said switching means further comprises a fuse section having a plurality of fuses, and a signal creating section which generates signals in accordance with cutting/non-cutting states of said plurality of fuses, and which supplies said signals to
clock input terminals of said clocked inverters to control operation of said clocked inverters;
said fuses are cut before said first step; and
one of said clocked inverters is selected and becomes active in accordance with cutting/non-cutting states of said plurality of fuses.
26. A method of accessing a semiconductor memory device according to claim 25, wherein
said fuse section further comprises a plurality of latch circuits which are coupled to said plurality of fuses, respectively, and which assume states in accordance with said cutting/non-cutting states of said fuses; and
signals which have been latched by said latch circuits are supplied to said signal creating section after said sixth step and before said seventh step.
27. A method of accessing a semiconductor memory device according to claim 26, wherein
said signal creating section comprises logical circuits, to which output signals of said latch circuits are supplied and which generate combination signals; and
said combination signals are respectively supplied to input terminals of said clocked inverters, one of said clocked inverters being selected by the combination signals after said sixth step and before said seventh step.
28. A method of accessing a semiconductor memory device according to claim 18, wherein
in said second step, said row address signals are inputted into said specification means in response to a transition of said basic clock signal; and
in said fifth step, said column address signals are inputted into said specification means in response to a transition of said basic clock signal.
29. A method of accessing a semiconductor memory device operable in a normal operation mode and a synchronous operation mode, said semiconductor memory device including
a memory cell array having a plurality of memory cells arranged in rows and columns;
specification means, into which address signals are input, for selecting at least some of said memory cells in said memory cell array as specified memory cells;
data input/output means for inputting data into the specified memory cells selected by said specification means, and for outputting data read out from the specified memory cells selected by said specification means;
selection means for sending address activation signals to said memory cell array, and for selecting one of said normal operation mode and said synchronous operation mode; and
control means for receiving a first control signal and a second control signal, and for controlling said specification means, said data input/output means and said selection means,
said first control signal for inputting said address signals into said specification means,
said second control signal switching said semiconductor memory device between said normal operation mode and said synchronous operation mode;
said method comprising:
in said normal operation mode,
a first step of asserting said first control signal;
a second step of, after said first control signal is asserted, inputting said address signals into said specification means;
a third step of selecting said specified memory cells in said memory cell array using said specification means; and
a fourth step of outputting data stored in said specified memory cells immediately after one of said specified memory cells is selected in said third step based on said address signals using said data input/output means; and
in said synchronous operation mode,
a first step of asserting said first control signal;
a second step of, after said first control signal is asserted, inputting said address signals into said specification means;
a third step of selecting said specified memory cells in said memory cell array using said specification means;
a fourth step of asserting said second control signal; and
a fifth step of outputting data stored in said specified memory cells from said data input/output means in synchronism with a basic clock signal N basic clock cycles, N being .gtoreq.2, after said second control signal is asserted and said basic
clock signal transitions.
30. A method of accessing a semiconductor memory device according to claim 29, wherein
said address signals include row address signals and column address signals input after said row address signals; and
said first control signal includes a row enable signal for inputting row address signals into said specification means and a column enable signal for, after a row address is determined by said specification means using an input of said row
address signals, inputting said column address signals into said specification means.
31. A method of accessing a semiconductor memory device according to claim 29, wherein
said address signals include at least row address signals; and
said first control signal includes at least a row enable signal for inputting row address signals into said specification means.
32. A method of accessing a semiconductor memory device according to claim 29, wherein
said address signals include at least column address signals; and
said first control signal includes at least a column enable signal for inputting column address signals into said specification means.
33. A method of accessing a semiconductor memory device according to claim 29, wherein
said semiconductor memory device further includes delay means for generating delay signals, each of said delay signals having a delay time period equivalent to a different number of cycles of said basic clock signal and switching means for
receiving said delay signals, and for selecting one of said delay signals to control said outputting of said data; and
in said synchronous operation mode, after said third step and before said fourth step, the number of said N basic clock cycles is selected using said switching means.
34. A method of accessing a semiconductor memory device according to claim 28, wherein
said delay means includes count means for counting a number of cycles of said basic clock signal; and
said count means generates said delay signals by counting the number of cycles of said basic clock signal and, after said third step and before said fourth step in said synchronous operation mode, supplies said delay signals to said switching
means.
35. A method of accessing a semiconductor memory device according to claim 34, wherein
said count means includes shift registers for transferring a trigger signal in response to a signal synchronized with said basic clock signal and, after said third step and before said fourth step in said synchronous operation mode, supplies the
trigger signal to said switching means.
36. A method of accessing a semiconductor memory device according to claim 35, wherein
each of said shift registers includes clocked inverters which operate in response to said signal synchronized with said basic clock signal.
37. A method of accessing a semiconductor memory device according to claim 36, wherein
said switching means includes clocked inverters one of which is selected after said third step and before said fourth step in said synchronous mode and then becomes active; and
said number N of said basic clock cycles is determined by an output signal of a selected clocked inverter.
38. A method of accessing a semiconductor memory device according to claim 37, wherein
said switching means further comprises a fuse section having a plurality of fuses;
said fuses are cut before said first step in said synchronous operation mode; and
one of said clocked inverters is selected and becomes active in accordance with states of said plurality of fuses.
39. A method of accessing a semiconductor memory device according to claim 37, wherein
said switching means further comprises a fuse section having a plurality of fuses, and a signal creating section which generates signals in accordance with cutting/non-cutting states of said plurality of fuses, and which supplies said signals to
clock input terminals of said clocked inverters to control operation of said clocked inverters;
said fuses are cut before said first step in said synchronous operation mode; and
one of said clocked inverters is selected and becomes active in accordance with cutting/non-cutting states of said plurality of fuses.
40. A method of accessing a semiconductor memory device according to claim 39, wherein
said fuse section further comprises a plurality of latch circuits which are coupled to said plurality of fuses, respectively, and which assume states in accordance with said cutting/non-cutting states of said fuses; and
signals which have been latched by said latch circuits are supplied to said signal creating section after said third step and before said fourth step in said synchronous operation mode.
41. A method of accessing a semiconductor memory device according to claim 40, wherein
said signal creating section comprises logical circuits, to which output signals of said latch circuits are supplied and which generate combination signals; and
said combination signals are respectively supplied to input terminals of said clocked inverters, one of said clocked inverters being selected by the combination signals.
42. A method of accessing a semiconductor memory device according to claim 29, wherein said second control signal is a pulse signal and is not asserted after outputting of data from said data input/output means begins in said fifth step.
43. A method of accessing a semiconductor memory device according to claim 29, wherein
in said second step of said normal operation mode, said address signals are inputted into said specification means in response to a transition of said basic clock signal; and
in said second step of said synchronous operation mode, said address signals are inputted into said specification means in response to a transition of said basic clock signal.
44. A method of accessing a semiconductor memory device according to claim 30, wherein
said row enable signal is used for inputting said row address signals into said specification means in response to a transition of said basic clock signal; and
said column enable signal is used for inputting said column address signals into said specification means in response to a transition of said basic clock signal.
45. A method of accessing a semiconductor memory device according to claim 31, wherein
said row enable signal is used for inputting said row address signals into said specification means in response to a transition of said basic clock signal.
46. A method of accessing a semiconductor memory device according to claim 32, wherein
said column enable signal is used for inputting said column address signals into said specification means in response to a transition of said basic clock signal.
47. A method of accessing a semiconductor memory device which includes
a memory cell array having a plurality of memory cells arranged in rows and columns;
specification means, to which address signals are input, for selecting at least some of said memory cells in said memory cell array as specified memory cells;
data input/output means for inputting data into the specified memory cells selected by said specification means, and for outputting data read out from the specified memory cells selected by said specification means;
control means for receiving a first control signal and a second control signal, and for controlling said specification means and said data input/output means,
said first control signal for inputting said address signals into said specification means,
said second control signal for controlling outputting of data stored in said specified memory cells, read out from the memory cell array, from said data input/output means, said data stored in said specified memory cells being output from said
data input/output means in synchronism with a basic clock signal;
outputting of said data stored in said specified memory cells beginning a number of basic clock cycles N of said basic clock signal, N being a positive integer .gtoreq.2, after said second control signal is asserted, a different one of said data
stored in said specified memory cells being output at each of said basic clock cycles after outputting begins until a plurality of data is output; and
means for selecting said number of basic clock cycles N from a plurality of predetermined numbers of basic clock cycles;
said method comprising:
a first step of asserting said first control signal;
a second step of, after asserting said first control signal, inputting said address signals into said specification means;
a third step of selecting said specified memory cells in said memory cell array using said specification means;
a fourth step of selecting said number of basic clock cycles N from said plurality of predetermined numbers of basic clock cycles;
a fifth step of asserting said second control signal; and
after said fourth and fifth steps, a sixth step of outputting data stored in said specified memory cells from said data input/output means in synchronism with said basic clock signal N basic clock cycles after said second control signal is
asserted and said basic clock signal transitions.
48. A method of accessing a semiconductor memory device according to claim 47, wherein
in said second step, said address signals are inputted into said specification means in response to a transition of said basic clock signal.
49. A method of accessing a semiconductor memory device which includes
a memory cell array having a plurality of memory cells arranged in rows and columns;
specification means, to which address signals are input, for selecting at least some of said memory cells in said memory cell array as specified memory cells;
data input/output means for inputting data into the specified memory cells selected by said specification means, and for outputting data read out from the specified memory cells selected by said specification means;
control means for receiving a first control signal, and for controlling said data input/output means,
said first control signal for controlling outputting of data stored in said specified memory cells, read out from the memory cell array, from said data input/output means;
said data stored in said specified memory cells being output from said data input/output means in synchronism with a basic clock signal, outputting of said data beginning after a latency, after said first control signal is asserted, a different
one of said data stored in said specified memory cells being output at each basic clock cycle after outputting begins until a plurality of data is output; and
means for selecting said latency from a plurality of predetermined latencies, each of said plurality of predetermined latencies being equivalent to a different number of basic clock cycles;
said method comprising:
a first step of inputting said address signals into said specification means;
a second step of selecting said specified memory cells in said memory cell array based on said address signals inputted in said first step using said specification means;
a third step of generating signals corresponding to said plurality of predetermined latencies;
a fourth step of receiving said signals corresponding to said plurality of predetermined latencies generated in said third step and selecting a signal corresponding to one latency of said plurality of predetermined latencies;
a fifth step of asserting said first control signal; and
after said fourth and fifth steps, a sixth step of outputting data stored in said specified memory cells from said data input/output means in synchronism with said basic clock signal after a time delay of said one latency after said first control
signal is asserted and said basic clock signal transitions.
50. A method of accessing a semiconductor memory device which includes
a memory cell array having a plurality of memory cells arranged in rows and columns;
specification means, to which address signals are input, for selecting at least some of said memory cells in said memory cell array as specified memory cells;
data input/output means for inputting data into the specified memory cells selected by said specification means, and for outputting data read out from the specified memory cells selected by said specification means;
control means for receiving a first control signal, and for controlling said data input/output means,
said first control signal for controlling outputting of data stored in said specified memory cells, read out from the memory cell array, from said data input/output means;
said data stored in said specified memory cells being output from said data input/output means in synchronism with a basic clock signal, outputting of said data beginning after a latency, after said first control signal is asserted, a different
one of said data being output at each basic clock cycle after outputting begins until a plurality of data is output; and
means for selecting said latency from a plurality of predetermined latencies, each of said plurality of predetermined latencies being equivalent to a different number of basic clock cycles;
said method comprising:
a first step of inputting said address signals into said specification means;
a second step of selecting said specified memory cells in said memory cell array based on said address signals inputted in said first step using said specification means;
a third step of generating a signal corresponding to one latency of said plurality of predetermined latencies;
a fourth step of asserting said first control signal; and
after said third and fourth steps, a fifth step of outputting data stored in said specified memory cells from said data input/output means in synchronism with said basic clock signal after a time delay of said one latency after said first control
signal is asserted. |
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Claims |
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