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Claims  |
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What is claimed is:
1. A multi chip module comprising:
a semiconductor wafer;
a substrate having a plurality of contact members;
a silicon alignment plate with an etched opening configured to align the
wafer with the substrate; and
a force applying member for biasing the wafer against the substrate with
the contact members on the substrate in electrical communication with
contact locations on the wafer.
2. The module as claimed in claim 1 further comprising a housing for
retaining the wafer, the substrate, the alignment plate and the force
applying member.
3. A multi chip module comprising:
a semiconductor wafer;
a substrate having a plurality of contact members;
an alignment plate configured to align the wafer with the substrate; and
a compressible bladder for biasing the wafer against the substrate with the
contact members on the substrate in electrical communication with contact
locations on the wafer.
4. A multi chip module comprising:
a semiconductor wafer having a plurality of contact locations thereon;
a substrate having a plurality of contact members thereon, each contact
member comprising at least one projection adapted to penetrate a
respective contact location to a limited penetration depth;
an alignment plate configured to align the contact members with the contact
locations; and
a force applying member for biasing the wafer against the substrate.
5. The module as claimed in claim 4 wherein the contact members comprise
conductive layers bonded to the contact locations.
6. The module as claimed in claim 4 further comprising a plurality of
conductive adhesive layers formed between the contact members and contact
locations.
7. The module as claimed in claim 4 further comprising a housing configured
to retain the wafer and substrate, the housing comprising terminals in
electrical communication with the contact members.
8. A multi chip module comprising:
a plurality of semiconductor dice having a plurality of contact locations
thereon;
a substrate comprising a plurality of contact members configured to
establish electrical communication with the contact locations on the dice;
a plurality of conductive adhesive layers bonding and electrically
connecting the contact members to the contact locations;
an alignment plate including a plurality of alignment openings with the
dice placed therein in alignment with the contact members; and
a force applying member for biasing the dice against the substrate.
9. The module as claimed in claim 8 further comprising a sealed housing for
containing the dice, the substrate, the alignment plate and the force
applying member.
10. The module as claimed in claim 8 wherein the dice comprise chip scale
packages.
11. The module as claimed in claim 8 wherein the contact members comprise
etched pillars covered with conductive layers.
12. A multi chip module comprising:
a plurality of semiconductor dice comprising a plurality of contact
locations;
a substrate comprising a plurality of contact members configured to
establish electrical communication with the contact locations on the dice;
an alignment plate comprising a plurality of alignment openings with the
dice placed therein in alignment with the contact members; and
a compressible bladder for biasing the dice against the substrate.
13. The module as claimed in claim 12 wherein the contact members comprise
bumps formed on tape attached to the substrate.
14. A multi chip module comprising:
a housing comprising a plurality of input/output terminals;
a substrate mounted to the housing comprising a plurality of contact
members in electrical communication with the terminals, the contact
members comprising microbumps mounted to a flexible tape attached to the
substrate;
an alignment plate attached to the housing in alignment with the substrate
and including an alignment opening;
a semiconductor wafer placed through the opening against the substrate with
contact locations on the wafer in electrical communication with the
contact members on the substrate.
15. The module as claimed in claim 14 further comprising a force applying
member for biasing the wafer against the substrate.
16. The module as claimed in claim 14 wherein the contact members are
bonded to the contact locations.
17. A multi chip module comprising:
a housing comprising a plurality of input/output terminals:
a substrate mounted to the housing, the substrate comprising a plurality of
contact members in electrical communication with the terminals;
an alignment plate on the housing and including an alignment opening; and
a semiconductor wafer comprising a plurality of contact locations, the
wafer placed through the opening and against the substrate with the
contact members bonded to the contact locations with a conductive
adhesive.
18. A multi chip module comprising:
a housing comprising a plurality of input/output terminals;
a substrate mounted to the housing, the substrate comprising a plurality of
contact members in electrical communication with the terminals, the
contact members comprising etched members covered with conductive layers;
an alignment plate on the housing and including an alignment opening; and
a semiconductor wafer comprising a plurality of contact locations, the
wafer placed through the opening and against the substrate with the
contact members in electrical communication with the contact locations.
19. The module as claimed in claim 18 wherein the alignment plate comprises
silicon.
20. The module as claimed in claim 18 wherein the contact members are
bonded to the contact locations with conductive adhesive layers.
21. A multi chip module comprising:
a housing comprising a plurality of input/output terminals;
a substrate mounted to the housing comprising a plurality of contact
members in electrical communication with the terminals;
an alignment plate mounted to the housing in alignment with the substrate
and including a plurality of alignment openings;
a plurality of semiconductor dice placed through the openings such that
contact locations on the dice are in electrical communication with the
contact members on the substrate; and
a force applying member for biasing the dice against the substrate, the
force applying member comprising a material selected from the group
consisting of silicone, butyl rubber, and fluorosilicone.
22. The module as claimed in claim 21 wherein the dice comprise known good
dice.
23. The module as claimed in claim 21 wherein the dice comprise chip scale
packages.
24. The module as claimed in claim 21 wherein the contact members are
bonded to the contact locations.
25. The module as claimed in claim 21 wherein the contact members comprise
microbumps mounted to a flexible tape attached to the substrate.
26. An assembly comprising:
a housing comprising a plurality of input/output terminals;
a silicon substrate mounted to the housing and having a plurality of
contact members comprising etched pillars covered with conductive layers
in electrical communication with the terminals,
an alignment plate placed on the substrate having an alignment opening
formed therethrough;
a semiconductor wafer placed through the alignment opening so that the
contact members establish electrical communication with contact locations
on the wafer;
a force applying member for biasing the wafer against the substrate.
27. The module as claimed in claim 26 wherein the wafer is thinned prior to
being placed in the alignment opening.
28. The assembly as claimed in claim 26 further comprising a cover
sealingly attached to the housing.
29. The assembly as claimed in claim 26 wherein the conductive layer is
bonded to the contact locations.
30. An assembly comprising:
a housing comprising a plurality of input/output terminals;
a substrate mounted to the housing and having a plurality of contact
members in electrical communication with the terminals, the contact
members comprising microbumps mounted to a flexible tape attached to the
substrate;
an alignment plate placed on the substrate having an alignment opening
formed therethrough;
a semiconductor wafer placed through the alignment opening so that the
contact members establish electrical communication with contact locations
on the wafer;
a force applying member for biasing the wafer against the substrate.
31. The assembly as claimed in claim 30 wherein the contact members are
attached to the contact locations using a conductive adhesive.
32. An assembly comprising:
a housing comprising a plurality of input/output terminals;
a substrate mounted to the housing and having a plurality of contact
members in electrical communication with the terminals;
an alignment plate placed on the substrate having an alignment opening
formed therethrough;
a semiconductor wafer placed through the alignment opening so that the
contact members establish electrical communication with contact locations
on the wafer;
a force applying member for biasing the wafer against the substrate; and
an underfill layer formed in a gap between the substrate and wafer.
33. An assembly comprising:
a housing comprising a plurality of input/output terminals;
a substrate mounted to the housing, the housing comprising a plurality of
contact members in electrical communication with the terminals,
an alignment plate placed on the substrate having an a plurality of
alignment openings formed therethrough;
a plurality of semiconductor dice placed through the alignment openings,
each die comprising a plurality of contact locations;
a plurality of conductive adhesive layers bonding and electrically
connecting the contact members on the substrate with the contact locations
on the dice; and
a force applying member for biasing the wafer against the substrate.
34. The assembly as claimed in claim 33 wherein the dice comprise tested
known good dice.
35. The assembly as claimed in claim 33 wherein the dice comprise bare
dice.
36. The assembly as claimed in claim 33 wherein the dice comprise chip
scale packages. |
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Claims |
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Description |
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FIELD OF THE INVENTION
This invention relates generally to semiconductor packaging and
particularly to the packaging of a semiconductor wafer or tested,
singulated dice to form a multi chip module (MCM).
BACKGROUND OF THE INVENTION
A multi chip module (MCM) is a semiconductor package that includes bare
semiconductor dice. Typically, the multi chip module includes an
interconnect substrate for mounting and interconnecting the dice, and a
housing for sealing and protecting the dice. The interconnect substrate
can include contact members that establish electrical communication with
bond pads or other contact locations on the dice. In addition, the
interconnect substrate can include interconnect circuitry that provides an
electrical path to the contact members and to input/output terminals for
the module.
One contact technology that is utilized to establish electrical
communication between the contact members on the interconnect substrate
and the bond pads on the dice, is known as "flip chip bonding". With flip
chip bonding, the dice are formed with raised bond pads having solder
bumps. For forming a multi chip module, the dice are mounted face down to
the interconnect substrate and the solder bumps are bonded to
corresponding contact members on the interconnect substrate. Typically for
flip chip bonding, the contact members on the interconnect substrate are
flat metal pads.
One shortcoming of flip chip bonding is that the solder bumps and contact
members on the substrate must have a minimum size and pitch to accommodate
formation of a reliable electrical connection. In general, the dimensions
of the bumps and contact members must be oversized to accommodate
misalignment between the dice and substrate. Because of this requirement,
the module must be formed with a relatively large surface area. Also the
density of the dice can be limited by the large number of bond pads
required by some dice.
In addition to density limitations, a temperature differential can develop
between the dice and the interconnect substrate due to heat generated
during operation of the integrated circuits formed on the dice. Since the
solder bumps are constrained in the x, y and z directions, stress
fractures can develop as a result of the temperature differential. The
stress fractures can cause an unreliable electrical connection between the
dice and substrate and can cause the mechanical bond between the dice and
substrate to loosen.
Because of density and alignment limitations, alternate methods have been
developed for forming multi chip modules. One prior art method of forming
multi chip modules that does not utilize flip chip bonding is disclosed in
U.S. Pat. No. 5,189,505 to Bartelink. This method includes forming contact
members on the substrate comprising a post and a flexible membrane.
Conductors formed on the substrate have one of their ends supported by the
posts. Identical contact members are formed on the dice and can be bonded
to the contact members on the substrate with a solder ball. This
arrangement allows the posts and conductors to flex to accommodate
misalignment between the substrate and dice. In general, this type of
contact member is relatively complicated and requires an expensive and
complex manufacturing procedure.
In view of the foregoing, a need exists for improved methods for
constructing multi chip modules. In particular, a module is needed in
which alignment can be effected between the dice and interconnect
substrate even with a dense array of dice having a large number of closely
spaced bond pads. In addition, the module must be able to accommodate a
temperature differential between the dice and interconnect substrate
without detriment to the electrical and mechanical connection
therebetween.
SUMMARY OF THE INVENTION
In accordance with the invention, an improved multi chip module and a
method for making the multi chip module are provided. The multi chip
module, broadly stated, includes: a semiconductor wafer containing
multiple semiconductor dice; an interconnect substrate having contact
members adapted to establish an electrical connection to the dice; and an
alignment plate for aligning the wafer and the interconnect substrate. The
multi chip module also includes a sealed housing and a force applying
member for biasing the wafer against the interconnect substrate. The force
applying member can be formed as a compressible bladder or as a layer of
an elastomeric material compressed within the housing.
The interconnect substrate can be formed of a semiconductor material, such
as silicon, with etched contact members covered with a conductive layer.
Alternately, the interconnect substrate can include microbump contact
members formed on a flexible tape similar to multi layered TAB tape. In
either case, the contact members on the interconnect substrate can be
bonded to contact locations on the dice (e.g., bond pads) using heat,
ultrasound or a conductive adhesive. In addition, conductors can be formed
on the interconnect substrate in electrical communication with the contact
members. The conductors can include contact pads that can be electrically
connected to input/output terminals on the housing by wire bonding, or
using mechanical-electrical connectors.
The alignment plate can also be formed of a semiconductor material such as
silicon. The alignment plate includes an etched alignment opening for
aligning the wafer with the interconnect substrate. Additionally, etched
alignment members on the alignment plate and interconnect substrate can be
provided for aligning the alignment plate with the interconnect substrate.
In an alternate embodiment, singulated dice rather than an entire wafer are
used to construct the multi chip module. In the alternate embodiment, the
alignment plate includes a plurality of alignment openings for aligning
the singulated dice with corresponding contact members on the interconnect
substrate. The singulated dice preferably have been tested and certified
as known good dice (KGD). Furthermore, the singulated dice can be in bare
form or can be contained in chip scale packages.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic perspective view illustrating components of a multi
chip module constructed in accordance with the invention;
FIG. 2 is a schematic cross sectional view of a multi chip module
constructed in accordance with the invention;
FIG. 3 is an enlarged cross sectional view taken along section line 3--3 of
FIG. 2 illustrating a contact member for the multi chip module shown in
FIG. 2 and its electrical connection to a bond pad on a semiconductor die;
FIG. 3A is a perspective view of a portion of FIG. 3 illustrating the
contact member;
FIG. 4 is an enlarged cross sectional view equivalent to FIG. 3 of an
alternate embodiment contact member for the multi chip module shown in
FIG. 2;
FIG. 5 is a schematic perspective view illustrating an alternate embodiment
alignment plate for an alternate embodiment multi chip module;
FIG. 6 is a schematic cross sectional view of the alternate embodiment
multi chip module;
FIGS. 7A-7D are schematic cross sectional views illustrating process steps
in forming a contact member for the multi chip module of FIG. 2; and
FIGS. 8A-8D are schematic cross sectional views illustrating process steps
in forming the alignment plate for the multi chip module of FIG. 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIGS. 1 and 2, a multi chip module 10 (FIG. 2) constructed in
accordance with the invention is shown. The multi chip module 10 comprises
an assembly that includes a semiconductor wafer 12, an alignment plate 14,
and an interconnect substrate 16. As shown in FIG. 2, the multi chip
module 10 also includes a housing 20 and a force applying member 22.
The semiconductor wafer 12 is mounted circuit side down and includes a
plurality of semiconductor dice 18. The interconnect substrate 16 is
adapted to establish electrical communication with the dice 18 on the
wafer 12. The alignment plate 14 is adapted to align the wafer 12 with the
interconnect substrate 16.
The semiconductor wafer 12 can be a standard wafer having identical
semiconductor dice 18. Alternately, some of the dice 18 can be configured
to perform a desired circuit function (e.g., memory) while other dice are
configured to perform a different function (e.g., address). By forming the
multi chip module 10 with an entire semiconductor wafer 12, a dense array
of dice 18 can be provided. The wafer 12 can also be provided with a
standard outline and thickness and one or more flats 23. Alternately, the
wafer 12 can be thinned from its backside using a planarization process
such as chemical mechanical planarization (CMP) or etching. By thinning
the wafer 12, the multi chip module 10 can be formed with a reduced
thickness. A representative thickness for the wafer 12 can be from 4 to
28.5 mils.
The alignment plate 14 includes an alignment opening 24 having a peripheral
outline that corresponds to the peripheral outline of the wafer 12. The
peripheral size of the alignment opening 24 is slightly larger than the
peripheral size of the semiconductor wafer 12. Preferably, the alignment
opening 24 has a diameter that is only about 5 to 25 .mu.m larger than the
diameter of the wafer 12. In the assembled multi chip module 10 this tight
tolerance helps to provide a close x and y direction registration between
the wafer 12 and the interconnect substrate 16.
The alignment plate 14 can be formed of a semiconductor material, such as
silicon, or of a material such as ceramic, or silicon nitride, having a
coefficient of thermal expansion (CTE) that is close to the CTE of the
semiconductor wafer 12. In addition, as will be further explained, with
the alignment plate 14 formed of silicon, the alignment opening 24 can be
formed using an etching process. In addition, by using an anisotropic etch
process to form the alignment opening 24, the sidewalls of the opening
will be sloped or tapered to facilitate guiding the wafer 12 into
alignment with the interconnect substrate 16.
The alignment plate 14 can be formed with a multi-sided peripheral outline
that is smaller than the outer circumference of the interconnect substrate
16. In the assembled multi chip module 10 (FIG. 2), the smaller outline of
the alignment plate 14 permits access to contact pads 26 formed along the
periphery of the interconnect substrate 16. As will be further explained,
the contact pads 26 are configured for making an electrical connection
between the housing 20 and the interconnect substrate 16.
Still referring to FIG. 1, the interconnect substrate 16 includes a
plurality of contact members 28. The contact members 28 are formed on the
interconnect substrate 16 in patterns that match the patterns of the bond
pads 30 (FIG. 3) on the semiconductor dice 18. In addition, the contact
members 28 are in electrical communication with conductors 32 formed on
the interconnect substrate 16. The conductors 32 are in electrical
communication with the contact pads 26. During assembly of the multi chip
module 10, electrical paths such as wire bonds are formed between the
contact pads 26 on the interconnect substrate 16 and input/output
terminals 42 (FIG. 2) on the housing 20.
The contact members 28 can also include penetrating projections 34 (FIG. 3)
adapted to penetrate into the bond pads 30 (FIG. 3) on the dice 18 to a
self limiting penetration depth. As will be further explained, the contact
members 28 and penetrating projections 34 can be formed integrally with
the interconnect substrate 16 using an etching process. Such a process
permits the contact members 28 to be formed accurately in a dense array.
As shown in FIG. 1, the interconnect substrate 16 can also include two or
more alignment posts 36 that mate with corresponding alignment pockets 38
in the alignment plate 14. In the assembled multi chip module 10 (FIG. 2),
the alignment posts 36 and alignment pockets 38 align the alignment plate
14 with the interconnect substrate 16. The alignment posts 36 and
alignment pockets 38 can be formed with tolerances as previously specified
that insure a tight x and y registration between the interconnect
substrate 16 and the alignment plate 14.
As shown in FIG. 2, the housing 20 of the multi chip module 10 is a
container adapted to contain the interconnect substrate 16, alignment
plate 14 and wafer 12. In the assembled multi chip module 10, the
interconnect substrate 20 mounts to the bottom surface of the housing 20
and the alignment plate 14 mounts to the interconnect substrate 14. If
desired, the alignment plate 14 can be attached to the interconnect
substrate 16 using a suitable adhesive.
The housing 20 can be formed of a material, such as plastic, molded into
the desired size and shape. The housing 20 can also be formed of laminated
ceramic or other insulating material formed in the desired size and shape.
A cover 40 can be sealingly attached to the housing 20 to provide a
sealable container.
As previously stated, the housing 20 includes a plurality of input/output
terminals 42. The input/output terminals 42 are in electrical
communication with conductive traces 44 formed within the housing 20. The
conductive traces 44 can be formed using techniques that are known in the
art such as 3D molding or metallization. The conductive traces 44 are
configured for electrical connection to the contact pads 26 on the
interconnect substrate 16. This electrical connection can be formed by
wire bonding bond wires 46 to the conductive traces 44 and to the contact
pads 26. Alternately, mechanical-electrical connectors 48 (FIG. 3) such as
spring clips or slide connectors can be used to establish electrical
communication between the conductive traces 44 and input/output terminals
42 on the housing 20, and the contact pads 26 for the interconnect
substrate 16. As yet another alternative, a conductive elastomer, such as
a z-axis strip (i.e., z-strip) can be used to form an electrical path.
Additionally, TAB tape in electrical contact with the contact pads 26 on
the interconnect substrate 16 and with the conductive traces 44 on the
housing can be used to form the electrical path.
In the assembled multi chip module 10, the wafer 12 is aligned with the
interconnect substrate 16 by the alignment plate 14. In addition, the
force applying member 22 is compressed within the housing 20 and is
adapted to press the wafer 12 against the interconnect substrate 16. The
force applying member 22 can be formed as a compressible bladder. This
type of compressible bladder is available from Paratech of Frankfort, Ill.
under the trademark "MAXI FORCE AIR BAG". Alternately the force applying
member 22A (FIG. 6) can be formed of a resilient elastomeric material such
as silicone, butyl rubber, or fluorosilicone; in foam, gel, solid or
molded configurations. Suitable elastomeric materials include "PORON"
available from Rogers or "BISCO" available from a Dow Chemical subsidiary.
The force applying member 22 can also be formed as a metal or plastic
spring member such as a wave spring, leaf spring, bellview washer or
compression spring.
In FIG. 2 the contact members 28 on the interconnect substrate 16 are
illustrated schematically with a larger than actual size. However, as will
be further explained, the contact members have a height of only about
1-100 .mu.m and would not be visible without a magnifying lens.
Referring to FIG. 3, the electrical connection between the contact members
28 on the interconnect substrate 16 and the bond pads 30 on the dice 18 is
shown. Each contact member 28 includes an insulating layer 50 and a
conductive layer 52. As will be further explained, with the interconnect
substrate 16 formed of silicon, the insulating layer 50 can be a grown or
deposited oxide such as SiO.sub.2.
The conductive layer 52 can be formed of a metal that can be readily bonded
to the bond pads 30 on the dice 18. The bond pads 30 are typically formed
of a thin layer of aluminum embedded in a passivation layer 54. The
conductive layer 52 can be formed of aluminum, copper, titanium, tungsten,
tantalum, platinum, molybdenum, cobalt, nickel, gold, iridium or alloys of
these metals. The conductive layer 52 can also be a metal silicide or a
conductive material such as polysilicon. In addition, the conductive layer
52 can be formed as a bi-metal stack.
The conductive layer 52 can be formed using a metallization process
including deposition (e.g., CVD), followed by photopatterning and etching.
The conductive layer 52 for each contact member 28 is in electrical
communication with a corresponding conductor 32 formed on the interconnect
substrate 16. The conductive layer 52 and conductors 32 can be formed at
the same time using the same metallization process. Alternately, the
conductive layer 52 can be formed of a different metal using a separate
metallization. The contact pads 26 for the conductors 32 can also be
formed using the same or a different metallization process and can be
formed with a wire bondable metallurgy.
Still referring to FIG. 3, with the force applying member 22 pressing
against the wafer 12, the penetrating projections 34 of the contact
members 28 penetrate into the bond pads 30 and pierce any native oxide
present to establish an electrical connection. However, the penetration
depth of the projections 34 is limited by the stop plane provided by the
top surface of the contact member 28. This limited penetration depth helps
to prevent damage to the bond pads 30. In addition, the separation
provided by the raised contact members 28 helps to clear any particulate
matter present between the wafer 12 and the interconnect substrate. As
clearly shown in FIG. 3A, the penetrating projections 34 can be formed as
elongated blades such that the current is spread out over a larger area.
In addition, from one to several penetrating projections 34 can be formed
on each contact member 28. Also, the penetrating projections 34 can be
formed in a parallel spaced array as shown, or in different patterns
(e.g., cross, circular, T-shape). For bond pads 30 that are bumped the
contact members 28 can be formed as disclosed in U.S. Pat. No. 5,592,736,
incorporated herein by reference.
The contact members 28 in addition to establishing an electrical connection
to the bond pads 30 can also be used to mechanically bond the wafer 12 to
the interconnect | | |
