A method of manufacturing a polysilicon plug in an integrated circuit semiconductor device wherein the polysilicon plug is selectively doped to act as a resistive load or alternatively to act as a diode load. The polysilicon load can be used in an SRAM memory cell.
The method of fabricating a semiconductor nonvolatile storage device of this invention includes the steps of: forming an element region and an element isolation region on a semiconductor substrate; forming a memory gate insulation film by sequentially layering a tunnel oxide film, a silicon nitride film and a top oxide film on the device region; forming a memory gate electrode on the memory gate insulation film; forming heavily doped diffusion regions at element region portions self-aligned on opposite sides of the memory gate electrode; forming an interlayer insulator over the whole surface of the semiconductor substrate; forming contact holes in the interlayer insulator; forming interconnections passing through the contact holes and connecting with the memory gate electrode and the heavily doped diffusion regions; forming a passivating film over the whole surface of the semiconductor substrate including the interconnections by the plasma chemical vapor deposition process; forming openings for input/output terminals in the passivating film at positions thereof corresponding to the memory gate electrode and the heavily doped diffusion regions by plasma etching; and annealing the passivating film.
An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.
A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.
Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.
Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.
