A circuit provides a restart signal to indicate a zero crossing of a continuous varying signal. A zero phase signal is generalized based on a zero crossing of the continuous varying signal. The continuous varying signal is sampled and held in accordance with the zero crossing. The continuous varying signal is converted to complementary signals, and these complementary signals are in turn converted to a signal appropriate for CMOS circuits.
A servo demodulator (20) is provided for generating a track identification signal (148) and a position error signal (150) from a servo wedge signal, such as a filtered servo wedge signal (112), in response to the processing of the servo wedge signal by a read channel (18). The servo demodulator (20) includes a servo clock generation circuit (90), a position error signal circuit (92), and a track identification circuit (76). The servo clock generation circuit (90) generates a synchronous servo clock signal (102) in response to receiving a servo reference clock signal (110) and the filtered servo wedge signal (112). The synchronous servo clock signal (102) is provided to the read channel (18) for use in processing the servo wedge signal. The position error signal circuit (92) generates the position error signal (150) in response to receiving the synchronous servo clock signal (102) from the servo clock generation circuit (90) and a synchronously sampled servo wedge signal (114) from the read channel (18). The read channel (18) generates the synchronously sampled servo wedge signal (114) by using the synchronous servo clock signal (102) to synchronously sample the servo wedge signal. The track identification circuit (76) generates the track identification signal (148) in response to receiving a digital servo wedge signal (116) from the read channel (18).
A method and a signal processing unit are proposed, for converting an asynchronous discrete-time signal to a synchronous discrete-time signal by performing sector-based timing recovery. The timing recovery includes aligning an initial portion of the asynchronous discrete-time signal to a first portion of a predetermined signal, and a later portion of the asynchronous discrete-time signal to a second portion of a predetermined signal. Optionally, the method and signal processing unit further perform sector based gain control, and sector-based removal of any dc component.
A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes. The device comprises: a programmable equalizer, having a plurality of equalizing modes, receiving an original signal so as to output an equalized signal; a phase-locked loop, receiving a reference clock signal and a first control signal so as to output first sampling pulses and second sampling pulses; a data slicing device, coupled to the phase-locked loop and the programmable equalizer and receiving the first sampling pulses, the second sampling pulses and the equalized signal so as to output a first slicing signal and a second slicing signal; and a signal processing device, coupled to the data slicing device and receiving the first slicing signal and the second slicing signal so as to output the first control signal and a second control signal; wherein the signal processing device programs the programmable equalizer by using the second control signal so as to select an equalizing mode from the plurality of equalizing modes for the programmable equalizer.
