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Claims  |
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What is claimed is:
1. A system which permits an embedded megacell within an integrated circuit
to be tested using test vectors applied to input/output pins of the
integrated circuit without requiring dedicated input/output pins for the
test vectors, said system comprising:
custom designed digital logic circuitry formed within said integrated
circuit, said custom designed digital logic circuitry having inputs and
outputs which are connected to input/output pins of said integrated
circuit when said integrated circuit is operating in a normal operational
mode;
a standardized megacell module having independent functionality formed
within said integrated circuit and incorporated into said integrated
circuit so as to communicate and function in unison with said custom
designed digital logic circuitry, said megacell module having test inputs
and test outputs which are used to test functionality of said megacell
module, said test inputs and test outputs having no connections to
input/output pins of said integrated circuit when said integrated circuit
is operating in said normal operational mode;
a JTAG boundary scan data register which stores a test vector used to test
integrity of inputs and outputs of said integrated circuit, said boundary
scan data register having outputs;
selection circuitry having first inputs which receive said outputs from
said custom designed logic circuitry, second inputs which receive said
outputs from said boundary scan data register and third inputs which
receive said outputs from said megacell module, said selection circuitry
having outputs, said selection circuitry having selection inputs which
control which of said first inputs, said second inputs and said third
inputs are routed to said outputs of said selection circuitry;
a JTAG instruction register which stores instruction bits, selected ones of
said instruction bits provided to said selection inputs of said selection
circuitry to control which of said first inputs, said second inputs and
said third inputs of said selection circuitry are routed to said outputs
of said selection circuitry, said instruction bits controlled in said
normal operational mode to select said first inputs to route the outputs
of said custom designed logic circuitry to said output of said selection
circuitry, said instruction bits controlled in a JTAG boundary scan test
operational mode to select said second inputs to route said outputs from
said boundary scan data register to said outputs of said selection
circuitry, and said instruction bits controlled in a megacell test mode to
select said third inputs to route said outputs of said megacell to said
outputs of said selection circuitry;
a plurality of external pins connected to said outputs of said selection
circuitry, said outputs from said custom designed logic circuitry being
propagated to said external pins when said integrated circuit is operating
in said normal operational mode, said test outputs of said megacell module
being propagated to said external pins when said selected ones of said
instruction register bits are controlled to cause said integrated circuit
to operate in said megacell test mode of operation, said outputs from said
boundary scan data register being propagated to said external pins when
said selected ones of said instruction register bits are controlled to
cause said integrated circuit to operate in said JTAG boundary scan test
operational mode; and
at least one gate interposed between at least one of said input/output pins
of said integrated circuit and at least one selected test input of said
megacell, said at least one gate controlled by a megacell test signal from
said JTAG instruction register to communicate a signal on said at least
one of said input/output pins to said at least one selected test input of
said megacell when said megacell test signal is active and to force said
at least one selected test input of said megacell to a predetermined
inactive state when said megacell test signal is not active.
2. A system as defined in claim 1, further comprising a switching circuit
including first and second inputs and an output, said switching circuit
selecting between an input pin connected with said first input of said
switching circuit or said custom designed digital logic circuitry
connected with said second input of said switching circuit, said output of
said switching circuit being connected to said standardized megacell
module.
3. A system as defined in claim 2, wherein said switching circuit comprises
a multiplexer.
4. A method of testing a megacell within an integrated circuit having said
megacell as an embedded component of circuitry within said integrated
circuit, said megacell having at least one test output signal having no
connection external to said integrated circuit during normal operation of
said integrated circuit, said megacell having at least a first input and a
second input, said first input and said second input having no connections
external to said integrated circuit during normal operation, said
integrated circuit including logic which communicates signals to and
receives signals from said megacell during said normal operation of said
integrated circuit, said logic applying a signal to said first input of
said megacell during normal operation, said integrated circuit having a
plurality of signals which are provided as inputs to and outputs from said
logic via respective pins of said integrated circuit during said normal
operation of said integrated circuit, said method comprising:
applying a serial instruction to said integrated circuit via a JTAG input
pin to place said integrated circuit into a predetermined megacell test
mode such that said integrated circuit is no longer operating in said
normal mode of operation;
selectively disabling at least one of said plurality of output signals from
said logic to a respective first external pin of said integrated circuit;
selectively routing said test output signal from said megacell to said
respective first external pin of said integrated circuit;
selectively disabling said signal from said logic to said first input to
said megacell and applying a test input signal to said first input of said
megacell via a second external pin of said integrated circuit to stimulate
said megacell to perform a test operation;
selectively routing a signal from a third external pin of said integrated
circuit to said second input of said megacell during said test operation
and selectively forcing said second input of said megacell to a
predetermined fixed logic level during said normal operation; and
monitoring said test output signal from said megacell at said respective
first pin of said integrated circuit during said test operation.
5. A system for testing a megacell within an integrated circuit having said
megacell as an embedded component of circuitry within said integrated
circuit, said megacell having at least first and second inputs and at
least one output which are not connected to external pins of said
integrated circuit during a normal mode of operation of said integrated
circuit, said integrated circuit further including logic, said integrated
circuit having a plurality of signals which are provided as normal input
signals to and normal output signals from said logic on respective
external pins of said integrated circuit during said normal operation of
said integrated circuit, said integrated circuit further including JTAG
boundary scan testing circuitry, said system comprising:
a JTAG input pin, wherein a serial instruction is applied to said JTAG
input pin and communicated to said boundary scan testing circuitry, said
boundary scan testing circuitry responsive to said serial instruction to
place said integrated circuit into one of a predetermined megacell test
mode of operation, a boundary scan test mode of operation, or a normal
mode of operation;
a first signal pin of said integrated circuit which is interconnected with
said logic when said integrated circuit is operating in said normal mode
of operation;
a first selectable electrical path from said first pin to said first input
of said megacell, wherein a test input signal applied to said first pin
when said integrated circuit is in said megacell test mode of operation is
communicated to said megacell via said selectable electrical path to
thereby stimulate said megacell to perform a test operation and to
generate a test output signal, said selectable electrical path blocked
when said integrated circuit is operating in said normal mode of operation
to force said first input of said megacell to a predetermined fixed logic
level;
a second pin of said integrated circuit;
a second selection circuit connected between said second pin of said
integrated circuit and said second input of said megacell, said second
selection circuit providing a path from said second pin to said second
input of said megacell when said integrated circuit is in said megacell
test mode of operation, said second selection circuit providing a path
from said logic when said integrated circuit is in said normal mode of
operation;
a third pin of said integrated circuit; and
a selection circuit coupled to said third pin of said integrated circuit
which receives said test output signal from said megacell, which receives
one of said plurality of output signals from said logic, and which
receives a signal from said boundary scan test circuitry, said selection
circuit providing a selected output signal to said third pin of said
integrated circuit, said selected output signal being said test output
signal when said integrated circuit is in said test mode of operation upon
application of said serial instruction on said JTAG input pin, said
selected output signal being said one of said output signals from said
logic when said integrated circuit is in said normal mode of operation,
said selected output signal being a boundary scan test signal from said
boundary scan test circuitry when said integrated circuit is in said
boundary scan test mode of operation. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improvements in testing of integrated
circuits. Specifically, the invention involves a method and apparatus for
testing a megacell within an application specific integrated circuit
"ASIC" at the chip level.
2. Description of Related Art
The increasing complexity of circuit designs and new integrated circuit
packaging techniques leads to an ever increasing problem of testing
integrated circuits and printed circuit boards. Software testing of
digital hardware is constantly improving, however the complexity of the
circuitry makes testing more difficult unless the components are designed
with testability in mind.
One method for testing circuitry which has received notable attention is
the IEEE 1149.1 Boundary-Scanned Standard originated by the International
Joint Tests Action Group (JTAG), (hereby incorporated by reference). One
implementation of this standard involves designing components (e.g.,
integrated circuits) for serial boundary-scanned testing by providing
shift-register elements daisy chained to form a path around the periphery
of an integrated circuit component. The idea behind the serial testing is
to shift serial data into and through a number of integrated circuit
components. The serial data is applied to inputs of known circuitry to
effect outputs as determined by the circuit functions. A master testing
circuit compares the return data to an expected result (i.e., a result
which is dependent upon the functions of the known circuitry). In other
words, the serial data inputs applied to the circuit being tested produces
known outputs if the circuit is functioning properly. If the data stream
returned to the master testing circuit is not as expected, then a
malfunction in the circuit is detected by the testing circuit. A careful
analysis (under software control) of the deviations in the data stream may
isolate any malfunctions within a circuit.
Boundary-scanned testing of components, as briefly explained above, can
also be expanded to testing of a very large scale integrated (VLSI)
circuitry such as an ASIC. An ASIC includes internal logic circuitry which
is normally inaccessible via the output pins supplied on the IC package.
Such internal logic circuitry within the ASIC is typically vendor-supplied
as a module having defined inputs and outputs, and is commonly referred to
as a megacell. In some circuit boards, the test inputs and outputs for the
vendor-supplied megacell within the ASIC are connected to special pins on
the IC package so that the megacell is accessible for testing purposes by
the manufacturer via external pins on the IC package. However, the extra
pins required to test the cell are typically of no use during normal
implementation and operation of the IC. Furthermore, the additional test
pins sometimes require the manufacturer to increase the IC package to the
next larger size die and or package because of the increased number of
pins. Thus, the IC package takes additional printed circuit board real
estate and costs are increased because a larger die size is generally more
expensive.
Furthermore, the standard JTAG specification allows a megacell within an
ASIC to be surrounded internally with JTAG cells. However, use of this
test architecture is incompatible with the way a vendor typically tests
megacells supplied by the vendor. That is, megacell vendors generally have
a standard test for their megacells. While the standard test vectors and
testing methods provided by the vendor to test a megacell are flexible
enough to allow for alternate pin ordering when testing their megacells,
it is cost prohibitive for a vendor to change the functionality of the
standard test. For example, a standard vendor test might be serially
loaded through the JTAG port and applied in parallel to the megacell but
this would be cost prohibitive since it would multiply the test time by
twice the length of the JTAG chain.
SUMMARY OF THE INVENTION
A JTAG interface is used, in accordance with one aspect of the present
invention to load a custom JTAG instruction which will bring the test
inputs and outputs for a vendor-supplied megacell within an ASIC to the
output pins in place of the normal signals provided on the output pins for
use by the fabricator of the ASIC in his chip level testing of that ASIC.
Thus, extra pins are not required to test the cell. This saves pins and
prevents the manufacturer from having to go to the next larger die size
and or package size because of additional test pins. Thus, printed circuit
board real estate is reduced, and costs are reduced because the smaller
die size is generally less expensive. The JTAG interface is not used in
the manner it was intended (i.e., as the sole interface to the tester).
Instead, it is used to place the ASIC in a test mode which allows a
vendor's standard megacell test to run, without adding new pins.
Under one aspect, the present invention is a system which provides for a
reduced number of external pins on an integrated circuit (IC) package
having JTAG test capability. The system comprises custom designed digital
logic circuitry formed within the IC package. The custom designed digital
logic circuitry has inputs and outputs. The system further comprises a
standardized megacell module having independent functionality formed
within the IC package and incorporated into the IC package so as to
communicate and function in unison with the custom designed digital logic
circuitry. The megacell module has test inputs and test outputs which are
used to test functionality of the megacell module. The system also
includes a JTAG boundary scan data test register having outputs which
stores a test vector used to test integrity of inputs and outputs of the
IC package. In addition, the system comprises first selection circuitry
having first inputs connected to at least one of the outputs of the data
test register and at least one of the test outputs of the megacell module,
where the first selection circuitry further receives a first selection
input and provides one of the first inputs as an output based upon the
first selection input; and second selection circuitry having second inputs
connected to the output of the first selection circuitry and to at least
one of the outputs of the custom designed digital logic circuitry, where
the second selection circuitry further receives a second selection input
and provides one of the second inputs as an output based upon the second
selection input. The system of the invention additionally comprises a JTAG
instruction register which stores instruction bits, and wherein the
instruction bits are used to determine the first selection input to the
first selection circuitry and the second selection input to the second
selection circuitry. Finally, the system includes a plurality of external
pins connected as outputs of the second selection circuitry so that the
test outputs of the megacell module are provided on the external pins when
the instruction register is set to cause the first and second selection
circuitry to propagate the megacell module test inputs and outputs to the
external pins.
Under a further aspect, the invention is a method of testing a megacell
within an integrated circuit having the megacell as an integral component
of circuitry within the integrated circuit. The megacell has at least one
test output signal having no connection external to the integrated circuit
during operation of the integrated circuit. The integrated circuit has a
plurality of signals which are provided as outputs on respective pins of
the integrated circuit during the operation of the integrated circuit. The
method comprises applying a serial instruction to the integrated circuit
via a JTAG input pin to place the integrated circuit into a predetermined
test mode; selectively disabling one of the plurality of output signals
from a respective first pin of the integrated circuit; selectively routing
the test output from the megacell to the respective first pin of the
disabled output signal; applying a test input to the megacell via a second
pin of the integrated circuit to stimulate the megacell to perform a test
operation; and monitoring the test output of the megacell at the
respective first pin of the integrated circuit.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a schematic block diagram which illustrates the configuration of
a JTAG test circuit.
FIG. 2 is a schematic block diagram which shows an IC circuit having a
megacell with test input/output terminals connected to external pins of
the IC.
FIG. 3 is a state diagram showing the operation of the TAP controller
circuit used to control the JTAG test circuit.
FIG. 4 is a schematic block diagram showing an improved JTAG test circuit
which provides a connection of an internal megacell with an external pin.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a schematic block diagram showing an integrated circuit (IC) chip
100 configured for testing using a JTAG IEEE 1149.1 daisy-chain
boundary-scan serial testing system. The exemplary JTAG system shown in
FIG. 1 comprises a master pattern generator/comparator 102 which outputs a
data/instruction signal over a line 105, a mode signal over a line 107,
and a clock signal over a line 109. It should be understood that according
to conventional terminology, the data/instruction signal line 105 is also
referred to as the TDI signal line, the mode signal line 107 is referred
to as the TMS signal line, and the clock signal line 109 is referred to as
the TCK signal line. The output lines 105, 107, and 109 of the pattern
generator/comparator 102 connect to external input pins extending from the
IC 100 so that a TAP controller state machine 110 within the IC 100
receives the signals via the lines 105, 107, and 109.
The TAP controller state machine 110 connects to a data shift register 115
via a serial data line 117 and a clock enable line 119. The TAP controller
state machine 110 further connects to an instruction shift register 120
via a serial instructions line 122 and a clock enable line 124. It should
be noted here that, typically, the TDI line 105, the serial data line 117,
and the serial instructions line 122 are connected to a common node and
the lines 105, 117, and 122 differ only insofar as they are considered as
carrying data, instructions, or both.
The data shift register 115 is connected in parallel with a latched data
register 130, while the instruction shift register 120 connects in
parallel with a latched instruction register 140. Each of the bit storage
locations within the latched data register 130 connects to a first input
of a multiplexer within the IC 100. For example, as depicted in FIG. 1,
one of the storage locations of the latched data register 130 connects to
a first input of a 2:1 multiplexer 145 via a line 147. Similarly, each of
the storage locations within the latched data register 130 connects to an
input of a multiplexer within the IC 100; however, for simplicity of
illustration, only one multiplexer 145 is depicted in FIG. 1 as connected
to the latched data register 130.
The latched instruction register 140 connects in parallel to a decoder 150
which is used to decode the instructions stored within the latched
instruction register 140. The decoder 150 provides select output to each
of the JTAG multiplexers within the IC 100 (i.e., the multiplexers used to
provide JTAG forced output levels). However, again for simplicity of
illustration, the decoder 150 is shown in FIG. 1 to provide only a single
select output to the multiplexer 145 via a line 152.
A second input of the multiplexer 145 connects to the normal integrated
circuitry 160 within the IC 100 via a line 162. The normal integrated
circuitry 160 within the IC 100 is the circuitry which performs the
specified functions which the IC 100 carries out during normal operation
(i.e., when the IC 100 is not being tested). The output of a multiplexer
145 connects to an output pin on the surface of the IC 100 via a line 165.
The data shift register 115 and the instruction shift register 120
respectively output serial data and instruction lines 172, 174 as first
and second inputs to a 2:1 multiplexer 170 which, in turn, outputs a
serial data return line 175 to the pattern generator/comparator 102.
In operation, the pattern generator/comparator 102 generates a pattern of
data and/or instructions (typically called a test vector) which are
serially transmitted over the line 105 to the TAP controller state machine
110. The pattern generator/comparator 102 further provides a mode and a
clock signal to the TAP controller state machine 110 via the lines 107,
109, respectively. As will be described in greater detail below with
reference to FIG. 3, the TAP controller state machine 110 responds to the
mode and clock signals to shift the data or instructions provided on the
line 105 into either the data shift register 115 (i.e., when data are
provided along the line 105) or into the instruction shift register 120
(i.e., when instructions are provided over the line 105). The data which
is shifted into the data shift register 115 and the instructions which are
shifted into the instruction shift register 120 are serially clocked into
their respective shift registers 115, 120 under the control of the TAP
controller state machine 110. Thus, for example, if 70 data bits are to be
shifted into the data shift register 115 and 30 instruction bits are to be
shifted into the instruction shift register 120, a total of 100 clock
cycles will be taken to shift each of the data and instruction bits into
their respective shift registers. Of course, as will be described in
greater detail below, additional clock cycles will be necessary to
transfer data from the pattern generator/comparator 102 to the TAP
controller state machine 110 and to change the mode of the TAP controller
state machine 110 so that the TAP controller state machine 110 provides
the appropriate control signals on the clock enable lines 119, 124.
Once the appropriate data for testing the designated inputs and outputs of
the IC 100 are shifted into the shift registers 115, 120, the shift
registers 115 and 120 parallel latch the data and instructions contained
within the shift registers 115, 120 into the respective latched registers
130, 140. The instructions latched into the register 140 are decoded by
the decoder 150 to select the appropriate output of the multiplexer 145,
as well as any other JTAG multiplexers (not shown) within the IC 100. As
briefly described above, each of the JTAG multiplexers (e.g., the
multiplexer 145 shown in FIG. 1) receives a JTAG input which is connected
to the latched data register 130. Thus, for example, the multiplexer 145
is enabled by the decoder 150 via the line 152 to select the input 147
connecting to a storage location within the register 130. Thus, the output
165 of the multiplexer 145 is forced to the bit value stored within the
register 130. In this manner, the output connections of the IC 100 over
the line 165 may be tested for defects. For example, if the storage
location connected to the multiplexer 145 via the line 147 contains a high
voltage level bit (i.e., corresponding to a digital 1), then the output of
the multiplexer 145 along the line 165 should be detected at the output
pin of the IC 100 to be a digital 1. If this output pin does not generate
a digital 1, then the test circuitry to which the IC 100 is connected will
register an error so that the IC 100 may be designated as defective. This
test is performed for each of the inputs and outputs designated by the
decoder 150 in response to the instructions loaded by the pattern
generator/comparator 102.
Of course, although not depicted in FIG. 1, it will be understood that
multiple ICs may be connected in series in a daisy-chain configuration so
that the pattern generator/comparator 102 can shift in data and
instructions for multiple ICs at one time. Thus, the IC 100 includes a
multiplexer 170 which selectively shifts out the data passing through the
register 115 or the instructions passing through the register 120 via the
lines 172 or 174 under the control of the TAP controller state machine
110. Finally, the data output from the last IC is transferred back to the
pattern generator/comparator 102 via the serial return line 175.
FIG. 2 is a schematic block diagram which depicts an IC 200 including a
vendor-supplied megacell 210 in addition to normal integrated circuitry
220. The megacell 210 operates as a functional unit within the IC 200
which receives inputs from and provides inputs to the normal circuitry 220
via lines 225.
The vendor-supplied megacell 210 is distinguished from the normal circuitry
220 in that the vendor-supplied megacell 210 has a standardized structure
and function provided by the vendor, while the normal circuitry is custom
designed by an ASIC designer. Thus, the megacell module has an independent
functionality (i.e., the megacell could be used to perform the same
function in a variety of different surrounding circuit configurations so
that this functionality is substantially independent from the other
circuitry within the IC 200). Furthermore, a separate set of test vectors
than those used to test the overall IC 200 are typically used to
separately test the functionality of the megacell 210.
Thus, for example, an ASIC designer uses standard functional logic blocks
such as UARTS, phase locked loops, etc., as a part of the ASIC design. An
ASIC vendor supplies structure for these standard functional logic blocks,
which the ASIC designer incorporates into a custom ASIC. These standard
functional blocks are referred to as megacells, and the megacell vendor
typically supplies test vectors which are used by the chip foundry during
the manufacturing process to test the megacell within the ASIC. Typically,
the ASIC can be tested as an entire unit, but if malfunctions are
discovered in the entire unit, it will be difficult to determine if the
malfunctions are due to custom circuitry whose structure is provided by
the ASIC designer or due to the cell vendor-supplied megacell circuitry.
For this reason, the megacells are tested independently using the test
vectors provided by the cell vendor. Additionally, the ASIC designer need
not expend the effort to exhaustively test the megacell since this testing
will be done via the vendor supplied tests.
However, as depicted in FIG. 2, in order to test a megacell such as the
megacell 210, test outputs from the megacell 210 require multiple output
pins 235 on the exterior surface of the ASIC 200. The vendor-supplied test
vectors are applied to the test inputs 230, and the resulting pattern on
the test outputs 235 is measured to determine if the megacell is
functioning correctly. The testing of the megacell functionality is
typically performed at the chip foundry (i.e., as a test after
fabrication), but is not necessary after the chip is in normal operational
use. Thus, for example, only the operational inputs and outputs 240 would
be used when the IC 200 is implemented within a circuit during normal
operation. Thus, the output pins 235 are superfluous during normal
operation of the IC 200. As will be described in greater detail with
reference to FIG. 4 below, the present invention provides for a reduction
of the number of output pins on an IC package which incorporates a
megacell circuit. The savings afforded by the present invention could be
significant (e.g., on the order of one or two dozen pins could be
eliminated) so that a more cost effective (i.e., smaller) die size and IC
package could be used.
FIG. 3 is a state diagram which illustrates the operation of the TAP
controller 110 in response to control signals provided on the mode and
clock lines 107, 109. The TAP controller state machine 110 begins in an
idle state 300 which constitutes a controller state between scan
operations. Once entered, the TAP controller 110 will remain in the idle
state 300 as long as the TMS is held low. In the idle state 300, activity
in selected test logic occurs only when certain instructions are present
as is well understood in the art. For instructions loaded in the
instruction register 140 that do not cause functions to execute in the
idle TAP controller state 300, all test data registers selected by the
current instruction shall retain their previous state (i.e., idle).
Furthermore, the instructions loaded within the instruction register 140
do not change while the TAP controller 110 is in the idle state 300.
When the TMS (mode signal along the line 107) is high and a rising edge is
applied to the TCK signal (clock over the line 109) the TAP controller 110
moves to a select data register scan state 305. The select data register
scan state 305 is a temporary controller state in which all test data
registers selected by the current instruction retain their previous state.
If TMS is held low while a rising edge is applied to TCK, then the TAP
controller 110 transitions to a capture data register state 315, while if
TMS is held high, and a rising edge is applied to TCK, then the TAP
controller state machine 110 transitions to a select instruction register
scan state 310.
If the TAP controller state machine 110 transitions into the capture data
register state 315, then, in this state, data may be parallel-loaded into
the data register 130 from the shift data register 115 on the rising edge
of TCK. If the JTAG test circuitry does not include a parallel-loaded data
register 130, or if capturing is not required for the selected test, then
the data register retains its previous state unchanged. Furthermore, the
bits stored within the instruction registers 140, 120 remain unchanged
while the TAP controller state machine 110 is in the captured data
register state 315. When the TAP controller 110 is in the capture data
register state 315 while TMS is held low and a rising edge is applied to
TCK, then the controller enters a shift data register state 320. However,
if TMS is held high while the rising edge is applied to TCK, then the TAP
controller state machine 110 transitions to an exit data register state
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