A data storage system is disclosed in which a 3-party hand-off protocol is utilized to maintain a single coherent logical image. In particular, the functionality of the data storage system is separated into distinct processing modules. There are at least three types of processing modules. These three kinds of processing modules function cooperatively to perform data storage operations via the 3-party hand-off protocol. At least two types of processing modules are required to cooperate in a hand-off manner to fully execute each data storage operation.

Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.

A cache system includes a processing device operative to access a main memory device, a primary cache coupled to the processing device and accessible from the processing device at faster speed than the main memory device, and a secondary cache coupled to the processing device via the primary cache and accessible from the processing device at faster speed than the main memory device, wherein the primary and secondary caches are configured such that first data is stored as a data entry in each of the primary and secondary caches when the first data is read from the main memory device in response to access from the processing device, and such that second data in the secondary cache is invalidated without invalidating the second data in the primary cache when a need arises to invalidate the second data in the secondary cache in response to access from the processing device.

An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.

A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.