A circuit, for incorporation into an electrical system, for providing a clock signal frequency to other circuitry such as a microprocessor and/or co-processor circuitry. The clock signal frequency varies its speed depending on the available voltage and current from a host power source. The circuit maximizes clock frequency by lowering the available voltage and increasing the available supply current. The circuit can therefore provide a higher clock speed and more current for switching transistors.
A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with the first device using the single wire bus.
A circuit arrangement including a voltage supply device, which has an output, and that provides a variable supply voltage, a supply-voltage-controlled clock generator, which is coupled to the output of the voltage supply device, and that provides a system clock signal having a variable effective system clock frequency, a circuit section having a supply terminal, which is coupled to the output of the voltage supply device, and a clock input, which receives the system clock signal, and a regulating device that determines a supply-voltage-dependent supply current value and detects the extent to which the supply current value lies within a predetermined current value range, and which is coupled to the voltage supply device such that the supply voltage is regulated based on whether the supply current value lies within the predetermined current value range.
A processor comprises a computation unit for performing an operation at a speed and a state unit, which has a state which changes in response to execution of an operation by the computation unit, the speed of the computation unit being controlled according to the state of the state unit. The state unit can e.g. be a capacitor or a unit with a thermal capacitance and controlling the speed of the computation unit can e.g. be effected via the frequency of a clock rate. In cryptographic applications the state unit is preferably so designed that the speed decreases when an operation is executed.
An interface device is connected to an OA (office automation) apparatus, such as a printer, a copier, a facsimile apparatus, a scanner or the like, and provides the OA apparatus with a new interface by being supplied with electric power from the OA apparatus. The interface device includes an extended-interface control unit for controlling an interface which is supplied with electric power from the OA apparatus and performs transmission/reception of data to/from the OA apparatus, a clock-frequency control unit for variably controlling an operational clock frequency for the interface device, and a unit for asking the OA apparatus about a current capacity suppliable from the OA apparatus. The clock-frequency control unit controls the clock frequency in order to suppress current consumption of the interface device within the current capacity.
A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with the first device using the single wire bus.
