Method for forming multileves interconnections for semiconductor fabrication

What is claimed is:

1. A method for use in fabricating a semiconductor device using a semiconductor substrate, comprising the steps of:

(a) forming over the semiconductor substrate a first patterned dielectric layer having a first dielectric material and having a first opening;

(b) filling the first opening with a first conductive material;

(c) forming over the first patterned dielectric layer and over the first conductive material a second dielectric layer having a second dielectric material;

(d) forming over the second dielectric layer a third dielectric layer having a third dielectric material;

(e) forming a patterned mask layer over the third dielectric layer:

(f) etching said third dielectric layer in accordance with the patterned mask layer to form a second opening over at least a portion of the first conductive material, the second opening exposing a portion of the second dielectric layer;

(g) removing said patterned mask layer after etching said third dielectric layer such that the exposed portion of the second dielectric layer protects the portion of the first conductive material beneath the second opening while said patterned mask layer is removed:

(h) etching the exposed portion of the second dielectric layer in accordance with the etched third dielectric layer at a rate greater than that for etching the third dielectric material in the third dielectric layer; and

(i) filling the second opening with a second conductive material.

2. The method of claim 1, wherein the second opening is greater in width than the first opening.

3. The method of claim 1, wherein the third dielectric material includes silicon dioxide.

4. The method of claim 3, wherein the second dielectric material includes silicon nitride.

5. The method of claim 1, wherein the patterned mask layer includes photoresist.

6. The method of claim 1, wherein the second dielectric material includes silicon nitride.

7. The method of claim 6, wherein the third dielectric material includes silicon dioxide.

8. The method of claim 1, wherein the filling step (b) includes the step of filling the first opening with a barrier layer and with a conductive layer such that the conductive layer is separated by the barrier layer from the first dielectric material of the first patterned dielectric layer.

9. The method of claim 8, wherein the conductive layer includes copper.

10. The method of claim 9, wherein the barrier layer includes titanium nitride.

11. The method of claim 8, wherein the second dielectric layer overlies a portion of the conductive layer, and

wherein the second dielectric material includes barrier material for the conductive layer.

12. The method of claim 11, wherein the second dielectric material includes silicon nitride.

13. The method of claim 11, wherein the first opening is greater in width than the second opening.

14. The method of claim 8, wherein the first patterned dielectric layer has a surface and wherein the filling step (b) includes the steps of:

(i) forming the barrier layer over the first patterned dielectric layer and within the first opening,

(ii) forming the conductive layer over the barrier layer and within the first opening, and

(iii) removing a portion of the barrier layer and a portion of the conductive layer from the surface of the first patterned dielectric layer.

15. The method of claim 14, wherein the removing step (b)(iii) includes the step of polishing the conductive layer and the barrier layer.

16. The method of claim 8, wherein the filling step includes the step of filling the second opening with a second barrier layer and with a second conductive layer such that the second conductive layer is separated by the second barrier layer from the third dielectric material of the third patterned dielectric layer.

17. The method of claim 16, wherein the second conductive layer includes copper.

18. The method of claim 17, wherein the second barrier layer includes titanium nitride.

19. The method as described in claim 1 wherein the third dielectric layer comprises an interconnect channel formed therein, the interconnect channel filled with the second conductive material.

20. The method as described in claim 2 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

21. The method as described in claim 4 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

22. The method as described in claim 1 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

23. The method as described in claim 8 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

24. The method as described in claim 9 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

25. The method as described in claim 10 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

26. The method as described in claim 11 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

27. The method as described in claim 14 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

28. The method as described in claim 15 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

29. The method as described in claim 16 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

30. The method as described in claim 17 wherein the third dielectric layer comprises and interconnect channel formed therein, the interconnect channel filled with the second conductive material.

31. A method for use in fabricating a semiconductor device using a semiconductor substrate, comprising the steps of:

(a) forming over the semiconductor substrate a first patterned dielectric layer having a first opening;

(b) filling the first opening with a first conductive material;

(c) forming a second dielectric layer over the first patterned dielectric layer and the first conductive material;

(d) forming a third dielectric layer over the second dielectric layer;

(e) forming a patterned mask layer over the third dielectric layer, wherein the patterned mask layer defines a second opening over at least a portion of the first conductive material;

(f) etching the third dielectric layer, in accordance with the patterned mask layer, to create the second opening, wherein the second opening exposes a portion of the second dielectric layer;

(g) removing the patterned mask layer;

(h) etching the second dielectric layer, in accordance with the third patterned dielectric layer, to remove the exposed portion of the second dielectric layer; and

(i) filling the second opening with a second conductive material.

32. The method of claim 31, wherein the second opening is greater in width than the first opening.

33. The method of claim 31, wherein the etching of the third dielectric layer of step (f) occurs at a rate greater than that for the second dielectric layer.

34. The method of claim 31, wherein the etching of the second dielectric layer of step (h) occurs at a rate greater than that for the third dielectric layer.

35. The method of claim 31, wherein the patterned mask layer includes photoresist.

36. The method of claim 31, wherein the third dielectric layer includes silicon dioxide.

37. The method of claim 36, wherein the second dielectric layer includes silicon nitride.

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FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices, and in particular, to the formation of interconnections for those devices.

BACKGROUND OF THE INVENTION

As devices are scaled to sub-micron dimensions, formation of reliable, sub-micron interconnections (interconnects) becomes increasingly important. Also important for sub-micron devices is the use of planarization technologies during interconnect and wiring formation, as well as other stages of device formation. Many current processes used to form interconnects are unable to form interconnects with a sub-micron width in production. These processes fail for one or more reasons as described below.

A common method of forming an interconnect includes the steps of: 1) forming a patterned dielectric layer having contact openings to at least one underlying layer; 2) depositing a metal layer over the patterned dielectric layer; 3) forming a patterned photoresist layer over the metal layer; 4) etching the metal layer to form the interconnect; and 5) removing the patterned photoresist layer. This method has several problems. First, the metal layer typically has poor step coverage that causes the metal to be thinner along the walls of the contact openings. The thin metal increases resistance and may break when the device is stressed, causing an open circuit. Second, there may be problems with etching. Wet chemical etchants etch isotropically and generally give insufficient dimensional control for sub-micron devices. Dry etching is typically used, but some metal layers, such as copper and gold, are difficult to plasma etch. Third, aluminum can be plasma etched, but it also has problems. The substrate is typically alloyed or subjected to at least one heat cycle after the aluminum has been deposited and patterned. The heat cycle may cause the aluminum to spike into the silicon substrate lying at the bottom of a contact opening. Also, aluminum can form hillocks during an alloy or other post-metalization heat cycles. The hillocks may protrude from the interconnect to make electrical connection between adjacent interconnects, thereby shorting the interconnects together. Fourth, even if the interconnects may be formed without any of the previous problems, a subsequent dielectric layer that covers the interconnects typically has step coverage problems between narrowly spaced interconnects or requires a planarization process sequence.

Selective Electroless Metal Deposition (SEMD) is a method capable of forming an interconnect with a sub-micron width. A dielectric layer is deposited and patterned to form a patterned dielectric layer having an interconnect channel. As used in this specification, an interconnect channel is a pattern within a dielectric layer, wherein part of the dielectric layer is etched away. The interconnect is subsequently formed within the interconnect channel. Before depositing the metal using SEMD, the surface upon which the metal is to be deposited typically needs a treatment within the interconnect channel, so that metal deposits within the interconnect channel but not on the patterned dielectric layer. A common technique for treating the surface includes very heavily doping the interconnect channel with silicon ions at a dose of at least 1.times.10.sup.16 ions/cm.sup.2. Another treatment method includes contacting the surface with an activating solution. Surface treatments typically involve at least one additional processing step and may cause processing complications. Surface treatments may not be completely effective, such that metal does not properly deposit within the interconnect channel. In addition, particles and other foreign materials may lie on the dielectric layer and act as nucleating sites during the metal deposition. Therefore, metal particles are typically formed on the patterned dielectric layer. The metal particles may cause electrical shorts or other defects within the device. The inconsistent effectiveness and complications of the surface treatments steps and the formation of metal particles have prevented the SEMD method from being used in a production mode.

Dual damascene is another method of forming interconnects within interconnect channels. A single dielectric layer is deposited and patterned using a two-step etch process. The first step etches most of the dielectric layer within contact openings and the second step etches the interconnect channels and the rest of the dielectric layer within the contact openings. The depth of the interconnect channels are difficult to control because of film deposition and etch nonuniformities. The interconnect channels may be too deep in the center of the wafer and too shallow near the edge of the same wafer, resulting in large variations of interconnect resistance across the wafer. Metal deposition is complicated because the contact openings may have an aspect ratio of 2:1, 3:1, or more. The high aspect ratio makes sputter depositions virtually impossible. A metal layer may be deposited by chemical vapor deposition within the contact openings and interconnect channels. However, widely used interconnect materials such as aluminum, copper, gold, and silver are not typically deposited by chemical vapor deposition in production. Polysilicon and tungsten may be deposited by chemical vapor deposition, but these materials have higher resistivities compared to aluminum, copper, gold, and silver and are not generally used as interconnect materials. The SEMD method may be used but has the previously discussed problems. In addition, the SEMD method may form a metal void if metal deposited within the interconnect channels seal off their underlying contact openings before the contact openings are filled.

Copper is typically not used as an interconnect material. Although copper has a relatively low cost and low resistivity, it has a relatively large diffusion coefficient into silicon dioxide and silicon. Copper from an interconnect may diffuse into the silicon dioxide layer causing the dielectric to be conductive and decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects should be encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared to silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and other interconnects and the substrate.

SUMMARY AND OBJECTS OF THE INVENTION

The embodiments of the present invention form an interconnect channel and an interconnect within a semiconductor device. In general, a first dielectric layer is deposited over a substrate and patterned to form a contact or via opening that is filled to form a contact or via plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact or via plug and is selectively etched to form an interconnect channel in the second dielectric layer. The first or second dielectric layers may comprise more than one individual dielectric layer. Preferably, the first dielectric layer acts as an etch stop when the second dielectric layer is selectively etched to form the interconnect channel. An interconnect layer is deposited over the second dielectric layer and within the interconnect channel. The substrate is polished with a polishing solution to remove that portion of the interconnect layer that lies on the second dielectric layer to form an interconnect within the interconnect channel. The interconnect layer may include a barrier layer and a metal layer. Additional interconnect levels may be formed in a similar manner. If needed, a diffusion barrier layer may be deposited before forming another interconnect level. A passivation layer is deposited over the uppermost interconnect level.

The embodiments have numerous benefits over prior art methods. The depth of the interconnect channels is easier to control because the first dielectric layer acts as an etch stop when selectively etching the second dielectric layer. A longer overetch during interconnect channel formation may be used without significantly etching the first dielectric layer. A copper interconnect may be formed, which may be thinner than an aluminum interconnect while giving the same or lower resistance. The polishing step forms a substantially planar substrate surface. Therefore, additional steps required for planarization schemes are not needed. One embodiment includes an encapsulated metal layer to provide more flexibility when selecting dielectric, metal, and plug materials.

A method for use in fabricating a semiconductor device using a semiconductor substrate is also described. A first patterned dielectric layer is formed over the semiconductor substrate. The first patterned dielectric layer has a first dielectric material and has a first opening. The first opening is filled with first conducti