A semiconductor manufacturing process in which a single crystal silicon semiconductor substrate is immersed in an oxidation chamber maintained at a first temperature preferably between 400.degree. and 700.degree. C. for a first duration. During the first duration, the oxidation chamber comprises a first ambient gas of N.sub.2 or Argon. Thereafter, the ambient temperature within the oxidation chamber is ramped to a second temperature in the range of approximately 600.degree. to 1100.degree. C. NH.sub.3 is then introduced into the oxidation chamber simultaneously with either NO or N.sub.2 O to form an oxynitride layer. Thereafter, a conductive gate structure is formed on the oxynitride layer and a source/drain impurity distribution is introduced into a pair of source/drain regions laterally displaced on either side of the channel region of the semiconductor substrate. The channel region is aligned with the conductive gate. Preferably, the resistivity of an epitaxial layer of the semiconductor substrate is in the range of approximately 10 to 15 .OMEGA.-cm. In one embodiment, the first ambient gas further includes 1 to 10% oxygen and the first temperature is in the range of approximately 600.degree. C. to 700.degree. C. In one embodiment, a thin base oxide film consisting essentially of silicon an oxygen is formed on the upper surface of the semiconductor substrate prior to the oxynitride formation. In one embodiment of the invention, the oxynitride layer is annealed in an N.sub.2 ambient at an anneal temperature in the range of approximately 600.degree. C. to 1100.degree. C. for a duration in the range of 30 seconds to 20 minutes.
The invention encompasses methods of forming pairs of transistor gates. In one aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) improving a lifetime of a low voltage tolerant transistor formed proximate the first substrate surface by cleaning the first substrate surface with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) forming a first transistor gate over the first substrate region and incorporating the first transistor gate into the low-voltage tolerant transistor; and d) forming a second transistor gate over the second substrate region and incorporating the second transistor rate into a high-voltage tolerant transistor. In another aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) cleaning at least one of the first and second substrate surfaces with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) after cleaning the at least one of the first and second substrate surfaces, forming a first oxide layer over the first and second substrate surfaces; d) removing the first oxide layer from over the first substrate surface while leaving the first oxide layer over the second substrate surface; and e) forming a second oxide layer over the first substrate surface.
A method for manufacturing a silicon carbide semiconductor device. In one embodiment, the method includes the following steps: a layer of silicon dioxide is formed on a silicon carbide substrate to create a silicon dioxide/silicon carbide interface and then nitrogen is incorporated at the silicon dioxide/silicon carbide interface for reduction in an interface trap density. The silicon carbide substrate, in one embodiment, includes a n-type 4H-silicon carbide.
In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.
A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).
In a method for manufacturing a semiconductor device where a silicon substrate is loaded in an oxidation furnace whose temperature is a first value, the temperature of the oxidation furnace is raised to a second value, and an oxidation operation is performed upon the silicon substrate to grow an essential silicon oxide layer on the silicon, a thickness ratio of an initial silicon oxide layer grown before the oxidation operation performing step to a less than 40 .ANG. thick gate silicon oxide layer formed by the initial silicon oxide layer and the essential silicon oxide layer is about 20 to 40 percent.
