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Claims  |
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We claim:
1. A memory device module comprising:
a plurality of integrated memory circuits fabricated on respective
semiconductor dies that are separate from each other each of the
integrated memory circuits receiving a plurality of input signals
including at least one address strobe signal, addresses, and other input
signals from external circuitry;
a plurality of enabling circuits each corresponding to one of the
integrated memory circuits, each enabling circuit operatively coupled to
its respective integrated memory circuit for receiving at least some of
the input signals, each enabling circuit being uniquely responsive to a
corresponding set of the input signals by outputting an enabling signal,
each enabling circuit's corresponding set of the input signals including
at least one of the other input signals; and
a plurality of function circuits each operatively coupled to a
corresponding one of the enabling circuits, each function circuit being
enabled by receiving the enabling signal from its respective enabling
circuit, whereby the respective function circuit of one of the integrated
memory circuits can be enabled without the respective function circuits of
the other integrated memory circuits being enabled.
2. The memory device module of claim 1 wherein each enabling circuit
comprises a NAND gate.
3. The memory device module of claim 1 wherein each enabling circuit's
corresponding set of the input signals includes a row address strobe
signal, a column address strobe signal, and a data signal.
4. The memory device module of claim 1 wherein each function circuit
comprises a redundant memory cell.
5. The memory device module of claim 1 wherein each integrated memory
circuit includes a memory array having a plurality of primary memory cells
and a plurality of redundant memory cells, wherein each function circuit
comprises an accessing circuit operatively coupled to the function
circuit's respective integrated memory circuit for receiving addresses,
each accessing circuit also being operatively coupled to the memory array
of its respective integrated memory circuit for accessing a primary memory
cell selected in accordance with a received address to communicate with
external circuitry, each accessing circuit being modifiable by the
enabling signal in accordance with a received address corresponding to an
inoperable primary memory cell in the accessing circuit's respective
memory array to access a redundant memory cell in the memory array instead
of the inoperable primary memory cell for communication with external
circuitry.
6. The memory device module of claim 1 wherein each enabling circuit
receives a plurality of the input signals, wherein each enabling circuit
comprises a plurality of fuse circuits each associated with a
corresponding one of the enabling circuit's plurality of the input
signals, each fuse circuit enabling its corresponding input signal to be
one of the input signals in the set of the input signals to which the fuse
circuit's respective enabling circuit is uniquely responsive.
7. The memory device module of claim 6 wherein each enabling circuit
further comprises a plurality of pass gates each associated with a
corresponding one of the enabling circuit's plurality of the input
signals, each pass gate being operatively coupled to a corresponding fuse
circuit for receiving an output signal, suppliable by each fuse circuit
each pass gate enabling its corresponding input signal upon receiving its
corresponding fuse circuit's output signal to be one of the input signals
in the set of the input signals to which the pass gate's respective
enabling circuit is uniquely responsive.
8. The memory device module of claim 7 wherein each fuse circuit includes
an anti-fuse.
9. The memory device module of claim 1 wherein said enabling circuits are
incorporated within said integrated memory circuits.
10. The memory device module of claim 1 wherein said function circuits are
incorporated within said integrated memory circuits.
11. A memory device module comprising:
a plurality of integrated memory circuits each receiving a plurality of
input signals including at least one address strobe signal, addresses and
other input signals from external circuitry;
a plurality of enabling circuits each corresponding to one of the
integrated memory circuits, each enabling circuit operatively coupled to
its respective integrated memory circuit for receiving at least some of
the input signals, each enabling circuit being uniquely responsive to a
corresponding set of the input signals by outputting an enabling signal,
each enabling circuit's corresponding set of the input signals including
at least one of the other input signals;
a plurality of function circuits each operatively coupled to a
corresponding one of the enabling circuits each function circuit being
enabled by receiving the enabling signal from its respective enabling
circuit, whereby the respective function circuit of one of the integrated
memory circuits can be enabled without the respective function circuits of
the other integrated memory circuits being enabled; and
a plurality of contacts accessible through direct electrical contact by
external circuitry wherein each of the input signals is coupled to at
least one of said contacts.
12. The memory device module of claim 11 wherein each integrated memory
circuit is provided on a die, each integrated memory circuit's die being
separate from the other integrated memory circuit's dies.
13. The memory device module of claim 11 wherein each enabling circuit
comprises a NAND gate.
14. The memory device module of claim 11 wherein each enabling circuit's
corresponding set of the input signals includes a row address strobe
signal, a column address strobe signal, and a data signal.
15. The memory device module of claim 11 wherein each function circuit
comprises a redundant memory cell.
16. The memory device module of claim 11 wherein the memory device module
each integrated memory circuit includes a memory array having a plurality
of primary memory cells and a plurality of redundant memory cells, wherein
each function circuit comprises an accessing circuit operatively coupled
to the function circuit's respective integrated memory circuit for
receiving addresses, each accessing circuit also being operatively coupled
to the memory array of its respective integrated memory circuit for
accessing a primary memory cell selected in accordance with a received
address to communicate with external circuitry, each accessing circuit
being modifiable by the enabling signal in accordance with a received
address corresponding to an inoperable primary memory cell in the
accessing circuit's respective memory array to access a redundant memory
cell in the memory array instead of the inoperable primary memory cell for
communication with external circuitry.
17. The memory device module of claim 11 wherein each enabling circuit
receives a plurality of the input signals, wherein each enabling circuit
comprises a plurality of fuse circuits each associated with a
corresponding one of the enabling circuit's plurality of the input
signals, each fuse circuit enabling its corresponding input signal to be
one of the input signals in the set of the input signals to which the fuse
circuit's respective enabling circuit is uniquely responsive.
18. The memory device module of claim 17 wherein each enabling circuit
further comprises a plurality of pass gates each associated with a
corresponding one of the enabling circuit's plurality of the input
signals, each pass gate being operatively coupled to a corresponding fuse
circuit for receiving an output signal suppliable by each fuse circuit,
each pass gate being adapted to enable its corresponding input signal upon
receiving its corresponding fuse circuit's output signal to be one of the
input signals in the set of the input signals to which the pass gate's
respective enabling circuit is uniquely responsive.
19. The memory device module of claim 18 wherein each fuse circuit includes
an anti-fuse.
20. The memory device module of claim 11 wherein said enabling circuits are
incorporated within said integrated memory circuits.
21. The memory device module of claim 11 wherein said function circuits are
incorporated within said integrated memory circuits.
22. A computer system comprising:
an input device;
an output device;
a processor operatively coupled to the input and output devices; and
a memory device module housed in a package and communicating through
circuitry external to the package with the processor, the memory device
module comprising:
a plurality of integrated memory circuits fabricated on respective
semiconductor dies that are separate from each other, each of the
integrated memorv circuits receiving a plurality of input signals
including at least one address strobe signal, addresses, and other input
signals;
a plurality of enabling circuits each corresponding to one of the
integrated memory circuits, each enabling circuit operatively coupled to
its respective integrated memory circuit for receiving at least some of
the input signals, each enabling circuit being uniquely responsive to a
corresponding set of the input signals by outputting an enabling signal,
each enabling circuit's corresponding set of the input signals including
at least one of the other input signals; and
a plurality of function circuits each operatively coupled to a
corresponding one of the enabling circuits, each function circuit being
enabled by receiving the enabling signal from its respective enabling
circuit, whereby the respective function circuit of one of the integrated
memory circuits can be enabled without the respective function circuits of
the other integrated memory circuits being enabled.
23. The computer system of claim 22 wherein each enabling circuit comprises
a NAND gate.
24. The computer system of claim 22 wherein each enabling circuit's
corresponding set of the input signals includes a row address strobe
signal, a column address strobe signal, and a data signal.
25. The computer system of claim 22 wherein each function circuit comprises
a redundant memory cell.
26. The computer system of claim 22 wherein each integrated memory circuit
includes a memory array having a plurality of primary memory cells and a
plurality of redundant memory cells, wherein each function circuit
comprises an accessing circuit operatively coupled to the function
circuit's respective integrated memory circuit for receiving addresses,
each accessing circuit also being operatively coupled to the memory array
of its respective integrated memory circuit for accessing a primary memory
cell selected in accordance with a received address to communicate with
the processor, each accessing circuit being modifiable by the enabling
signal in accordance with a received address corresponding to an
inoperable primary memory cell in the accessing circuit's respective
memory array to access a redundant memory cell in the memory array instead
of the inoperable primary memory cell for communication with the
processor.
27. The computer system of claim 22 wherein each enabling circuit receives
a plurality of the input signals, wherein each enabling circuit comprises
a plurality of fuse circuits each associated with a corresponding one of
the enabling circuit's plurality of the input signals, each fuse circuit
enabling its corresponding input signal to be one of the input signals in
the set of the input signals to which the fuse circuit's respective
enabling circuit is uniquely responsive.
28. The computer system of claim 27 wherein each enabling circuit further
comprises a plurality of pass gates each associated with a corresponding
one of the enabling circuit's plurality of the input signals, each pass
gate being operatively coupled to a corresponding fuse circuit for
receiving an output signal suppliable by each fuse circuit, each pass gate
being adapted to enable its corresponding input signal upon receiving its
corresponding fuse circuit's output signal to be one of the input signals
in the set of the input signals to which the pass gate's respective
enabling circuit is uniquely responsive.
29. The computer system of claim 28 wherein each fuse circuit includes an
anti-fuse.
30. The computer system of claim 22 wherein said enabling circuits are
incorporated within said integrated memory circuits.
31. The computer system of claim 22 wherein said function circuits are
incorporated within said integrated memory circuits.
32. A computer system comprising:
an input device;
an output device;
a processor operatively coupled to the input and output devices: and
a memory device module housed in a package and communicating through
circuitry external to the package with the processor, the memory device
module comprising:
a plurality of integrated memory circuits each receiving a plurality of
input signals including at least one address strobe signal, addresses, and
other input signals;
a plurality of enabling circuits each corresponding to one of the
integrated memory circuits, each enabling circuit operatively coupled to
its respective integrated memory circuit for receiving at least some of
the input signals, each enabling circuit being uniquely responsive to a
corresponding set of the input signals by outputting an enabling signal,
each enabling circuit's corresponding set of the input signals including
at least one of the other input signals;
a plurality of function circuits each operatively coupled to a
corresponding one of the enabling circuits, each function circuit being
enabled by receiving the enabling signal from its respective enabling
circuit, whereby the respective function circuit of one of the integrated
memory circuits can be enabled without the respective function circuits of
the other integrated memory circuits being enabled; and
a plurality of contacts accessible through direct electrical contact by
external circuitry wherein each of the input signals is coupled to at
least one of said contacts.
33. The computer system of claim 32 wherein each integrated memory circuit
is provided on a die, each integrated memory circuit's die being separate
from the other integrated memory circuit's dies.
34. The computer system of claim 32 wherein each enabling circuit comprises
a NAND gate.
35. The computer system of claim 32 wherein each enabling circuit's
corresponding set of the input signals includes a row address strobe
signal, a column address strobe signal, and a data signal.
36. The computer system of claim 32 wherein each function circuit comprises
a redundant memory cell.
37. The computer system of claim 32 wherein each integrated memory circuit
includes a memory array having a plurality of primary memory cells and a
plurality of redundant memory cells, wherein each function circuit
comprises an accessing circuit operatively coupled to the function
circuit's respective integrated memory circuit for receiving addresses,
each accessing circuit also being operatively coupled to the memory array
of its respective integrated memory circuit for accessing a primary memory
cell selected in accordance with a received address to communicate with
the processor, each accessing circuit modifiable by the enabling signal in
accordance with a received address corresponding to an inoperable primary
memory cell in the accessing circuit's respective memory array to access a
redundant memory cell in the memory array instead of the inoperable
primary memory cell for communication with the processor.
38. The computer system of claim 32 wherein each enabling circuit receives
a plurality of the input signals, wherein each enabling circuit comprises
a plurality of fuse circuits each associated with a corresponding one of
the enabling circuit's plurality of the input signals, each fuse circuit
enabling its corresponding input signal to be one of the input signals in
the set of the input signals to which the fuse circuit's respective
enabling circuit is uniquely responsive.
39. The computer system of claim 38 wherein each enabling circuit further
comprises a plurality of pass gates each associated with a corresponding
one of the enabling circuit's plurality of the input signals, each pass
gate being operatively coupled to a corresponding fuse circuit for
receiving an output signal suppliable by each fuse circuit, each pass gate
being adapted to enable its corresponding input signal upon receiving its
corresponding fuse circuit's output signal to be one of the input signals
in the set of the input signals to which the pass gate's respective
enabling circuit is uniquely responsive.
40. The computer system of claim 39 wherein each fuse circuit includes an
anti-fuse.
41. The computer system of claim 32 wherein said enabling circuits are
incorporated within said integrated memory circuits.
42. The computer system of claim 32 wherein said function circuits are
incorporated within said integrated memory circuits.
43. A memory module comprising a plurality of integrated memory circuits
fabricated on respective semiconductor dies that are separate from each
other, each of the integrated memory circuits receiving a plurality of
input signals, including at least one address strobe signal, addresses,
and other input signals from external circuitry, each of said integrated
memory circuits including an enabling circuit receiving at least one of
said input signals and being uniquely responsive to said at least one
input signal by outputting an enabling signal, each of said integrated
memory circuits further including a function circuit coupled to said
enabling circuit, said function circuit altering or augmenting the
operation of said integrated memory circuit responsive to said enabling
signal.
44. The memory module of claim 43 wherein each integrated memory circuit
includes a memory array having a plurality of primary memory cells and a
plurality of redundant memory cells, wherein each function circuit
comprises an accessing circuit operatively coupled to the function
circuit's respective integrated memory circuit for receiving addresses,
each accessing circuit also being operatively coupled to the memory array
of its respective integrated memory circuit for accessing a primary memory
cell selected in accordance with a received address to communicate with
external circuitry, each accessing circuit being modifiable by the
enabling signal in accordance with a received address corresponding to an
inoperable primary memory cell in the accessing circuit's respective
memory array to access a redundant memory cell in the memory array instead
of the inoperable primary memory cell for communication with external
circuitry.
45. The memory module of claim 43 wherein said enabling circuit receives a
plurality of said input signals, wherein each enabling circuit comprises a
plurality of fuse circuits each associated with a corresponding one of the
enabling circuit's plurality of the input signals, each fuse circuit
enabling its corresponding input signal to be one of the input signals in
the set of the input signals to which the fuse circuit's respective
enabling circuit is uniquely responsive.
46. A memory module comprising a plurality of integrated memory circuits
each receiving a plurality of input signals, including at least one
address strobe signal, addresses and other input signals from external
circuitry, each of said integrated memory circuits including an enabling
circuit receiving at least one of said input signals and being uniquely
responsive to said at least one input signal by outputting an enabling
signal, each of said integrated memory circuits further including a
function circuit coupled to said enabling circuit, said function circuit
altering or augmenting the operation of said integrated memory circuit
responsive to said enabling signal the memory module further comprising a
plurality of contacts accessible through direct electrical contact by
external circuitry wherein each of said input signals is coupled to at
least one of said contacts.
47. The memory module of claim 46 wherein each of said integrated memory
circuits is fabricated on a semiconductor die each of which is physically
separate from the dies of other integrated memory circuits.
48. The memory module of claim 46 wherein each integrated memory circuit
includes a memory array having a plurality of primary memory cells and a
plurality of redundant memory cells, wherein each function circuit
comprises an accessing circuit operatively coupled to the function
circuit's respective integrated memory circuit for receiving addresses,
each accessing circuit also being operatively coupled to the memory array
of its respective integrated memory circuit for accessing a primary memory
cell selected in accordance with a received address to communicate with
external circuitry, each accessing circuit being modifiable by the
enabling signal in accordance with a received address corresponding to an
inoperable primary memory cell in the accessing circuit's respective
memory array to access a redundant memory cell in the memory array instead
of the inoperable primary memory cell for communication with external
circuitry.
49. The memory module of claim 46 wherein said enabling circuit receives a
plurality of said input signals, wherein each enabling circuit comprises a
plurality of fuse circuits each associated with a corresponding one of the
enabling circuit's plurality of the input signals, each fuse circuit
enabling its corresponding input signal to be one of the input signals in
the set of the input signals to which the fuse circuit's respective
enabling circuit is uniquely responsive.
50. An integrated memory circuit, comprising:
an array of memory cells;
an accessing circuit allowing external communication of address, data and
other signals with said array;
an enabling circuit receiving as input signals at least some of said
address, data and other signals, said enabling circuit being uniquely
responsive to said input signals by outputting an enabling signal;
a function circuit coupled to said enabling circuit, said function circuit
altering or augmenting the operation of said array responsive to said
enabling signal; and
a plurality of contacts accessible through direct electrical contact by
external circuit wherein each of said input signals is coupled to at least
one of said contacts.
51. The integrated memory circuit of claim 50 wherein said memory array has
a plurality of primary memory cells and a plurality of redundant memory
cells, wherein said accessing circuit is operatively coupled to said
function circuit for receiving addresses, said accessing circuit also
being operatively coupled to said memory array for accessing a primary
memory cell selected in accordance with a received address to communicate
with external circuitry, said accessing circuit being modifiable by the
enabling signal in accordance with a received address corresponding to an
inoperable primary memory cell in said memory array to access a redundant
memory cell in the memory array instead of the inoperable primary memory
cell for communication with external circuitry.
52. The integrated memory circuit of claim 50 wherein said enabling circuit
receives a plurality of said input signals, wherein each enabling circuit
comprises a plurality of fuse circuits each associated with a
corresponding one of the enabling circuit's plurality of the input
signals, each fuse circuit enabling its corresponding input signal to be
one of the input signals in the set of the input signals to which the fuse
circuit's respective enabling circuit is uniquely responsive.
53. The integrated memory circuit of claim 50, further including a
programming circuit for selecting a combination of said address, data and
other signals to which said enabling circuit is to be uniquely responsive.
54. The integrated memory circuit of claim 50 wherein said programming
circuit may be programmed to select said combination of said address, data
and other signals after a plurality of said integrated memory circuits
have been combined and packaged in a memory module.
55. In a memory device module housed in a package, the memory device module
having a plurality of integrated memory circuits therein fabricated on
respective semiconductor dies that are separate from each other, each of
the integrated memory circuits receiving a plurality of input signals
including at least one address strobe signal, addresses, and other input
signals from external circuitry, each integrated memory circuit having a
plurality of primary memory cells and a plurality of redundant memory
cells, each integrated memory circuit being modifiable in accordance with
a received address upon receiving an enabling signal to access one of its
redundant memory cells instead of a primary memory cell associated with
the received address, a method for programming one of the integrated
memory circuits to access one of its redundant memory cells instead of a
primary memory cell for communication with external circuitry, the method
comprising:
determining an address corresponding to an inoperable primary memory cell
in one of the integrated memory circuits;
providing the determined address to the integrated memory circuit;
selecting a unique set of the input signals to which the memory device
module responds by providing an enabling signal to the integrated memory
circuit, the set including at least one of the other input signals;
providing each of the input signals in the set to the integrated memory
circuit so that it receives the enabling signal, whereby the integrated
memory circuit is modified in accordance with the determined address to
access a redundant memory cell instead of the inoperable primary memory
cell for communication with external circuitry.
56. The method of claim 55 wherein the step of selecting the unique set of
the input signals comprises, for each of the input signals which is to be
in the set, enabling the input signal to be in the set with a fuse.
57. The method of claim 55 wherein the step of selecting the unique set of
the input signals comprises, for each of the input signals which is to be
in the set, enabling the input signal to be in the set with an anti-fuse. |
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Claims |
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Description |
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FIELD OF THE INVENTION
This invention relates in general to integrated memory circuits, and in
particular to circuits and methods for enabling function circuits such as
redundant memory cells in integrated memory circuits.
BACKGROUND OF THE INVENTION
In conventional memories, multiple integrated memory circuits are sometimes
packaged together in a module referred to as a multiple memory device
module. For example, multiple integrated memory circuits implemented on
one or more dies can be packaged together in a multiple memory device
module such as a single in-line memory module (SIMM), a dual in-line
memory module (DIMM) and a multi-chip memory module (MCM). Of course,
other package types also work.
Each integrated memory circuit in a multiple memory device module typically
has one or more optional function circuits which can be enabled if
necessary. For example, a redundant memory cell in an integrated memory
circuit can be enabled to replace an inoperable memory cell having an
address which is typically determined during the manufacturing process.
Another typical optional function circuit allows for fine tuning of the
component values of circuit elements such as resistors and capacitors in
an integrated memory circuit. These redundant memory elements or other
optional function circuits are typically enabled by opening laser fuses or
shorting anti-fuses. For this reason, the redundant elements or function
circuits are generally enabled at the chip level before the chip has been
placed in a module. If a defect is found in a memory chip once the chip
has been placed in a module, either the memory chip must be removed from
the module for enabling the redundant elements or function circuits or the
redundant elements or function circuits must be enabled for all chips on
the module. For these reasons, memory device repair and the selection of
optional functions once memory chips have been assembled together in a
module has not been feasible for individual memory chips.
One approach to enabling a function circuit in an integrated memory circuit
packaged along with other integrated memory circuits in a multiple memory
device module might be to apply a high voltage to one of the input
terminals of the module. The high voltage would then generally be strobed
into the module with an address strobe signal such as CAS, and would be
applied to each integrated memory circuit in the module which shares the
same address strobe signal. Within each integrated memory circuit
receiving the high voltage, programmable elements, such as anti-fuses,
would be blown by the high voltage to enable the desired function circuit.
Thus, for example, if the high voltage was applied to the inputs of a
multiple memory device module receiving both a CAS1 signal and a CAS2
signal, and the high voltage was then strobed into the module with the
CAS1 signal, then the high voltage would be applied to each integrated
memory circuit in the module which shares the CAS1 signal. As a result,
the desired function circuit would be enabled in each integrated memory
circuit which shares the CAS1 signal. Of course, the CAS1 signal could
only go to one integrated memory circuit, in which case only the desired
function circuit in that integrated memory circuit would be enabled.
For the above reasons, it does not appear to be possible to enable a
desired function circuit in only one integrated memory circuit in a
multiple memory device module. In a typical multiple memory device module,
each integrated memory circuit has its own memory array which includes
memory cells arranged in rows and columns and associated redundant memory
cells typically arranged in rows. If a memory cell in a row in one of the
integrated memory circuits is inoperable, then the above-described
approach to repairing the inoperable memory cell would be to replace the
row it is in with an associated row of redundant memory cells. At the same
time, however, this approach would also replace operable memory cells in
the other integrated memory circuits in the multiple memory device module
with their associated rows of redundant memory cells. Consequently, in a
multiple memory device module having two integrated memory circuits which
share the same CAS signal, a row in one of the integrated memory circuits
would be replaced with an associated redundant row despite the fact that
the replaced row is not faulty.
This inability to isolate a faulty row in a single integrated memory
circuit in a multiple memory device module for replacement would reduce
the rate of success for repairing multiple memory device modules, since
each repair would cause many operable standard memory cells to be
unnecessarily replaced. Thus, for example, in a multiple memory device
module having eight integrated memory circuits, repairing one inoperable
standard memory cell would result in the replacement of one row of
standard memory cells in each of the eight integrated memory circuits with
an associated redundant row. If there is a 99% chance associated with each
redundant row that it does not contain an inoperable memory cell, then
there is a (0.99).sup.8 or only a 92% chance that all eight redundant rows
do not contain inoperable memory cells. During a typical manufacturing run
of thousands of multiple memory device modules, the difference between a
99% rate of successful repair and a 92% rate is obviously of great
significance.
Therefore, there is a need in the art for a circuit and method for
advantageously enabling a function circuit, such as a redundant memory
cell, in only one of the integrated memory circuits in a multiple memory
device module. Such a circuit and method should, when used to repair
multiple memory device modules with inoperable standard memory cells,
provide an increased rate of successful repair.
SUMMARY OF THE INVENTION
An inventive memory device module has a plurality of integrated memory
circuits each operatively coupled to a communication coupler in the
package for communicating with circuitry external to the package. Each
integrated memory circuit receives a plurality of input signals including
at least one address strobe signal, addresses, and other input signals
from external circuitry. The inputs may be received through externally
accessible contacts, or from a contactless interface such as a radio
frequency or optical signal interface. The module also includes an
enabling circuit, preferably including a NAND gate, corresponding to each
of the integrated memory circuits. Each enabling circuit is operatively
coupled to its respective integrated memory circuit to receive at least
some of the input signals. Each enabling circuit is uniquely responsive to
a corresponding set of the input signals by outputting an enabling signal.
Each set includes at least one of the other input signals. The module
further includes a function circuit corresponding to each of the enabling
circuits. Each function circuit is enabled by receiving an enabling signal
from its respective enabling circuit. Preferably, the function circuits
are redundant memory cells.
In this manner, the respective function circuit of one of the integrated
memory circuits is advantageously enabled without the respective function
circuits of the other integrated memory circuits being enabled.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a preferred computer system according to the
present invention including a memory device module.
FIG. 2 is a block diagram of the memory device module of FIG. 1 including
integrated memory circuits.
FIG. 3 is a block diagram of one of the integrated memory circuits of FIG.
2 including an enabling circuit.
FIG. 4 is a block, schematic and logic diagram of the enabling circuit of
FIG. 3 including fuse circuits and pass gates.
FIG. 5 is a schematic diagram of the fuse circuits of FIG. 4.
FIG. 6 is a schematic diagram of the pass gates of FIG. 4.
DETAILED DESCRIPTION OF THE INVENTION
In a preferred embodiment of the present invention shown in FIG. 1, a
computer system 10 includes an input device 12, such as a keyboard, and an
output device 14, such as a CRT monitor, both of which are operatively
coupled to a conventional processor 16. The computer system 10 further
includes a multiple memory device module 18 operatively coupled to the
processor 16. It will be understood by those with skill in the field of
this invention that the present invention is applicable to any multiple
memory device module, including those that comprise dynamic random access
memories (DRAMs) or static random access memories (SRAMs).
One embodiment of the memory device module 18 of FIG. 1 is shown in more
detail in FIG. 2. It includes a plurality of integrated memory circuits
20a and 20b operatively coupled to the processor 16 (not shown) to receive
address strobe signals RAS and CAS and addresses A<0:9> from the processor
16 (not shown), and to transfer data signals DQ<1:8> to and from the
processor 16 (not shown).
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