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Claims  |
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What is claimed is:
1. In a computer system, a computer implemented method of constructing scan
chains within an integrated circuit design, said method comprising the
computer implemented steps of:
a) accessing a first integrated circuit module design within said
integrated circuit design;
b) automatically detecting scan resources contained within said first
integrated circuit module design, said scan resources detected in step b)
referred to as a first inferred scan segment; and
c) adding said first inferred scan segment to a first existing scan chain
without altering said first inferred scan segment.
2. A method as described in claim 1 wherein said step b) comprises the step
of automatically detecting that said first integrated circuit module
design contains scan cells and scan routing resources between said scan
cells.
3. A method as described in claim 1 wherein said step b) comprises the step
of detecting annotations within said first integrated circuit module
design indicating the presence of said scan resources contained therein.
4. A method as described in claim 1 wherein said step c) comprises the step
of coupling access points associated with said first inferred scan segment
with said first existing scan chain, said access points including scan in,
scan out, and scan enable signal lines.
5. A method as described in claim 1 further comprising the steps of:
d) identifying a first user defined scan segment, said first user defined
scan segment including a member list of coupled scan cells and access
points to said member list, said access points including scan in, scan
out, and scan enable signal lines; and
e) adding said first user defined scan segment to said first existing scan
chain without altering said first user defined scan segment.
6. A method as described in claim 5 wherein said first existing scan chain
is associated with a first clock domain and further comprising the steps
of:
accessing a second integrated circuit module design within said integrated
circuit design;
automatically detecting scan resources contained within said second
integrated circuit module design, said scan resources detected referred to
as a second inferred scan segment;
adding said second inferred scan segment to a second existing scan chain
without altering said second inferred scan segment;
identifying a second user defined scan segment, said second user defined
scan segment including a member list of coupled scan cells and access
points to said member list, said access points including scan in, scan
out, and scan enable signal lines; and
adding said second user defined scan segment to said second existing scan
chain without altering said user defined scan segment, wherein said second
existing scan chain is associated with a second clock domain different
from said first clock domain.
7. In a computer system, a computer implemented method of constructing scan
chains within a hierarchical structured integrated circuit design, said
method comprising the computer implemented steps of:
a) determining a plurality of inferred scan segments, each inferred scan
segment associated with a separate integrated circuit module design within
said integrated circuit design;
b) accessing a plurality of user defined scan segments associated with said
integrated circuit design, each of said user defined scan segments
including a member list of coupled scan cells and access points to said
member list, said access points including scan in, scan out, and scan
enable signal lines; and
c) automatically constructing a first scan chain and a second scan chain,
said step c) comprising the steps of:
1) automatically linking inferred scan segments determined in step a) with
user defined scan segments accessed in step b) to form said first scan
chain, said inferred scan segments and said user defined scan segments of
said first scan chain being of a first common clock domain;
2) automatically linking inferred scan segments accessed in step a) with
user defined scan segments accessed in step b) to form said second scan
chain, said inferred scan segments and said user defined scan segments of
said second scan chain being of a second common clock domain, wherein said
first scan chain and said second scan chain are substantially balanced.
8. A method as described in claim 7 wherein said step c1) and said step c2)
do not alter said inferred scan segments during said linkings.
9. A method as described in claim 7 wherein said step c) is performed
pursuant to a user specification set scan path command.
10. A method as described in claim 7 wherein said first clock domain
includes clock signals that trigger on different edges and wherein said
steps c1) and c2) individually include the step of adding lock up latches
in clock signal paths between scan segments that are clocked with clock
signals that trigger on different edges.
11. A method as described in claim 7 wherein said step a) comprises the
step of, for each integrated circuit module design, detecting annotations
within said integrated circuit module design indicating the presence of an
inferred scan segment of said plurality of inferred scan segments.
12. In a computer system, a computer implemented method of constructing
scan chains within a hierarchical structured integrated circuit design,
said method comprising the computer implemented steps of:
a) accessing a user defined scan chain specification;
b) accessing a plurality of user defined scan segments associated with said
integrated circuit design, each of said user defined scan segments
including a member list of coupled scan cells and access points to said
member list, said access points including scan in, scan out, and scan
enable signal lines; and
c) automatically constructing a first scan chain and a second scan chain,
said first scan chain defined by said user defined scan chain
specification, said step c) comprising the steps of:
1) automatically linking a first group of user defined scan segments
accessed in step b) and listed in said user defined scan chain
specification to form said first scan chain, said first group of user
defined scan segments being of a first common clock domain; and
2) automatically linking a second group of user defined scan segments
accessed in step b) to form said second scan chain, wherein said first
scan chain and said second scan chain are substantially balanced.
13. A method as described in claim 12 wherein said second group of user
defined scan segments of said second scan chain are of said first common
clock domain.
14. A method as described in claim 12 wherein said second group of user
defined scan segments of said second scan chain are of a second common
clock domain different from said first common clock domain.
15. A method as described in claim 12 further comprising the step of d)
determining a plurality of inferred scan segments, each inferred scan
segment associated with a separate integrated circuit module design within
said integrated circuit design and wherein said step c 1) comprises the
step of automatically linking to said first scan chain inferred scan
segments determined in step d) that are listed in said user defined scan
chain specification.
16. A method as described in claim 15 wherein said step c2) comprises the
step of automatically linking to said second scan chain certain inferred
scan segments determined in step d) that are not linked in said first scan
chain.
17. A method as described in claim 16 wherein said step c1) and said step
c2) do not alter said inferred scan segments during said linkings.
18. A method as described in claim 15 wherein said step d) comprises the
step of detecting annotations within said separate integrated circuit
module designs indicating the presence of said plurality of inferred scan
segments.
19. In a computer system having a processor and a bus coupled to said
processor, a computer readable memory coupled to said bus wherein said
computer readable memory containing a set of instructions that when
executed causing said computer system to perform a method of constructing
scan chains within an integrated circuit design, said method comprising
the steps of:
a) accessing a first integrated circuit module design within said
integrated circuit design;
b) automatically detecting scan resources contained within said first
integrated circuit module design, said scan resources detected in step b)
referred to as a first inferred scan segment; and
c) adding said first inferred scan segment to a first existing scan chain
without altering said first inferred scan segment.
20. A computer readable memory as described in claim 19 wherein said step
b) comprises the step of automatically detecting that said first
integrated circuit module design contains scan cells and scan routing
resources between said scan cells.
21. A computer readable memory as described in claim 19 wherein said step
b) comprises the step of detecting annotations within said first
integrated circuit module design indicating the presence of said scan
resources contained therein.
22. A computer readable memory as described in claim 19 wherein said step
c) comprises the step of coupling access points associated with said first
inferred scan segment with said first existing scan chain, said access
points including scan in, scan out, and scan enable signal lines.
23. A computer readable memory as described in claim 19 further comprising
the steps of:
d) identifying a first user defined scan segment, said first user defined
scan segment including a member list of coupled scan cells and access
points to said member list, said access points including scan in, scan
out, and scan enable signal lines; and
e) adding said first user defined scan segment to said first existing scan
chain without altering said first user defined scan segment.
24. A computer readable memory as described in claim 23 wherein said first
existing scan chain is associated with a first clock domain and further
comprising the steps of:
accessing a second integrated circuit module design within said integrated
circuit design;
automatically detecting scan resources contained within said second
integrated circuit module design, said scan resources detected referred to
as a second inferred scan segment;
adding said second inferred scan segment to a second existing scan chain
without altering said second inferred scan segment;
identifying a second user defined scan segment, said second user defined
scan segment including a member list of coupled scan cells and access
points to said member list, said access points including scan in, scan
out, and scan enable signal lines; and
adding said second user defined scan segment to said second existing scan
chain without altering said user defined scan segment, wherein said second
existing scan chain is associated with a second clock domain different
from said first clock domain.
25. In a computer system having a processor and a bus coupled to said
processor, a computer readable memory coupled to said bus wherein said
computer readable memory containing a set of instructions that when
executed causing said computer system to perform a method of constructing
scan chains within a hierarchical structured integrated circuit design,
said method comprising the steps of:
a) accessing a user defined scan chain specification;
b) accessing a plurality of user defined scan segments associated with said
integrated circuit design, each of said user defined scan segments
including a member list of coupled scan cells and access points to said
member list, said access points including scan in, scan out, and scan
enable signal lines; and
c) automatically constructing a first scan chain and a second scan chain,
said first scan chain defined by said user defined scan chain
specification, said step c) comprising the steps of:
1) automatically linking a first group of user defined scan segments
accessed in step b) and listed in said user defined scan chain
specification to form said first scan chain, said first group user defined
scan segments being of a first common clock domain;
2) automatically linking a second group of user defined scan segments
accessed in step b) to form said second scan chain, wherein said first and
said second scan chain are substantially balanced.
26. A computer readable memory as described in claim 25 wherein said second
group of user defined scan segments of said second scan chain are of a
second common clock domain different from said first common clock domain.
27. A computer readable memory as described in claim 25 further comprising
the step of d) determining a plurality of inferred scan segments, each
inferred scan segment associated with a separate integrated circuit module
design within said integrated circuit design and wherein said step c1)
comprises the step of automatically linking to said first scan chain
inferred scan segments determined in step d) that are listed in said user
defined scan chain specification.
28. A computer readable memory as described in claim 27 wherein said step
c2) comprises the step of automatically linking to said second scan chain
inferred certain scan segments determined in step d) that are not linked
in said first scan chain.
29. A computer readable memory as described in claim 28 wherein said step
c1) and said step c2) do not alter said inferred scan segments during said
linkings.
30. A computer readable memory as described in claim 27 wherein said step
d) comprises the step of detecting annotations within said separate
integrated circuit module designs indicating the presence of said
plurality of inferred scan segments. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the field of computer aided design (CAD)
systems for integrated circuit (IC) designs. Specifically, the present
invention relates to the field of CAD systems for implementation of design
for test (DFT) circuitry.
(2) Prior Art
Complex integrated circuits (ICs) are designed with the use of computer
aided design (CAD) tools. Specifically, application specific integrated
circuits (ASICs) and field programmable gate array (FPGA) circuits are
designed using a variety of CAD tools. The development of IC custom
designs (e.g., ASICs and FPGA circuits) with the aid of CAD tools is
referred to as electronic design automation or EDA. Design, checking and
testing of large scale integrated circuits are so complex that the use of
programmed computer systems are required for realization of normal IC
designs. This is partly because the integrated devices are inherently
complex and partly because an IC design can be decomposed into simpler
functions and units which can be effectively processed by a computer
system. CAD systems are also used in IC designs because considerable
computation is required in order to achieve an efficient substrate layout
(e.g., placement) of the resultant IC design. The result of the
computerized design process is a detailed specification defining a complex
integrated circuit in terms of a particular technology. This specification
can be regarded as a template for the fabrication of the physical
embodiment of the integrated circuit using transistors, routing resources,
etc.
As part of the CAD system for fabricating ICs, design for test (DFT)
circuitry and techniques are utilized to integrate circuit elements into
an IC design which allow for circuit testability. Generally, DFT circuitry
can require the replacement of certain cells in an IC design with
specialized cells that allow for the application of test vectors (bit
strings) to circuitry within the IC design (e.g., "circuit stimulus").
Furthermore, the DFT circuitry also captures the output of the IC
circuitry in response to the circuit stimulus and reports this output for
comparison against a stored reference output. In one particular DFT
methodology, sequential cells are used to shift serial test vectors into
the IC design, apply the test vectors to the IC circuitry, capture the
circuitry's output and then serially shift the output data for comparison.
In this methodology, the DFT cells that serially shift in the test vectors
are referred to as scan cells and they are linked together to form scan
chains, a single scan chain receives input test vector data and supplies
the response data. A single IC design can contain multiple scan chains.
An IC design can contain many subdesigns (modules) which likewise can
contain subdesigns therein. Under this topology, the top level of an IC
design typically includes a hierarchical structure of interconnected
circuit modules. Furthermore, the various modules of an IC design are
typically assigned to and developed by different groups of people working
under common direction from top level designers and architects. It is
desirable to apply DFT circuitry throughout a hierarchical IC design.
Therefore it is desirable to apply DFT circuitry to the top level of the
IC design and also to any modules (subdesigns) located therein so that the
entire IC design can be properly tested. Since different modules of an IC
design can be independently developed, it would be desirable to allow
independent development and insertion of DFT circuitry for individual
modules.
Unfortunately, within prior art CAD systems that automatically construct
DFT circuitry, their scan architecture processes generally recognize: 1)
scan cells; and 2) complete scan chains that commence at a primary input
and end at a primary output of the "chip." Therefore, in constructing a
complete scan chain by integrating modules designs, any DFT routing
circuitry already present within a module is eliminated by prior art CAD
systems and scan paths within the module are then reconstructed using
heuristics pertinent to the CAD system and using configurations defined at
the top level design. This prior art approach is inefficient in that DFT
circuitry located within modules is removed and re-architected instead of
directly integrated in larger scan chains. This approach is also
inefficient in that same DFT circuitry located in replicated modules is
not re-used by the prior art CAD systems.
The above prior art approach is also problematic because it does not allow
DFT implementation to be spread among many module designers. It is
desirable to allow module designers to implement subdesign scan chains so
that the process of adding DFT circuitry can be spread among many designs.
By spreading the DFT implementation across modules, the overall time
required to generate the integrated DFT implementation in a hierarchical
design can be decreased and efficiency increased. Also, by allowing a
subdesigner to implement subdesign scan chains which are later used during
integration, certain risks associated with DFT integration (e.g., not
finding scan design rule violations earlier in the design flow) can be
reduced allowing the DFT integration to flow more smoothly with less
unexpected problems. Furthermore, since module designers are capable of
optimizing their designs, it is desirable not to remove and redesign
subdesign scan chains within existing modules because these modifications
can risk creating constraint violations within the modified modules. In
effect, the act of removing the scan chains and adding new scan structure
to an existing module, as done in the prior art, can violate specified
constraints that are otherwise satisfied by the original optimized module
design.
It is appreciated that some prior art CAD systems allow existing DFT
circuitry of a module to be manually presented and used by the top level
DFT design. Although this method provides some ability for the module
designers to provide DFT information for the top level DFT processes, the
requirement that this information be manually entered and maintained is
economically expensive for almost all IC designs.
Also, in certain DFT implementations, the time required to perform scan
insertion is relatively long. It is desired to provide a mechanism and
system allowing a user to observe certain results of the scan insertion,
for purposes of DFT designing, without requiring the full scan insertion
duration or making actual design modifications.
Accordingly, what is needed is a CAD system and mechanism for effectively
allowing top level DFT processes to automatically integrate DFT designs
located within modules in order to architect top level scan chains.
Further, what is needed is a CAD system and mechanism as above for
allowing automatic construction of scan chains within modules when none
currently exist. What is further needed is a mechanism and system allowing
a user to observe certain results of the scan insertion, for purposes of
DFT designing, without requiring the full scan insertion duration. Also,
what is needed is a system for allowing user specifications for
controlling the above processes. The present invention provides these
advantageous functionalities. Under the present invention, a designer of a
module within an IC design can independently generate a subdesign scan
chain that can be later used by the DFT processing of the top level.
Therefore, under the present invention, the module designer can
effectively "sign off" his or her work at the completion of the module
design and their completed and optimized modules do not need to be later
disrupted, and possibly risk constraint violations, during DFT processes
of the top level.
SUMMARY OF THE INVENTION
A system and method are described for architecting design for test
circuitry (e.g., scan architecting) within an integrated circuit design
having subdesigns (e.g., modules). The present invention system contains a
default operational mode (no user specification) and an operational mode
based on user specifications; within either mode, the system recognizes
and allows definition of subdesign scan chains which can be linked
together alone or with other scan elements to architect complex scan
chains (e.g., top level scan chains). Individual scan chains are
constructed using user defined scan segments and detected inferred
segments. Inferred segments are automatically detected if present within
IC module designs. When integrated into larger scan chains, the user
defined scan segments and the inferred scan segments are not modified
during linking.
The system includes specification, analysis, synthesis and reporting
processes which can be used in an IC design having a hierarchical
structure including modules. The specification process accesses a design
database and a script file and allows a user to define global scan
properties (scan style, number of chains, etc.), properties of a
particular scan chain (membership, name, etc.), test signals (scan-in,
scan-out, scan-enable, etc.), complex elements used as part of a scan
chain without requiring scan replacement, wires and latches forming
connections between scan elements; this information is associated with the
selected design database. The analysis processes reads the design database
and performs architecting of scan chains based on inferred scan elements
of the design and defined (e.g. specified) scan elements. During analysis,
the logic within the design database is not altered and an output script
is generated. The script generated by analysis indicates scan structures
that "will be," but do not currently exist. Specification and analysis can
be executed iteratively until a desired report is generated. The synthesis
processes alters the design database based on the scan chains architected
by analysis to implement the desired DFT circuitry. At any time, the
report processes generates a report of the existing scan structures within
a design database (e.g., "what is") without altering the design. By not
requiring synthesis to be executed until after the scan structures are
approved during specification-analysis iterations, repetition of the time
consuming synthesis process is avoided within the present invention.
Specifically, embodiments of the present invention include a computer
implemented method of constructing scan chains within a hierarchical
structured integrated circuit design, the method comprising the computer
implemented steps of: a) determining a plurality of inferred scan
segments, each inferred scan segment associated with a separate integrated
circuit module design within the integrated circuit design; b) accessing a
plurality of user defined scan segments associated with the integrated
circuit design, each of the user defined scan segments including a member
list of sequentially coupled scan cells and access points to the member
list, the access points including scan in, scan out, and scan enable
signal lines; and c) automatically constructing a first and a second scan
chain, the step c) comprising the steps of: 1) automatically linking
inferred scan segments determined in step a) with user defined scan
segments accessed in step b) to form the first scan chain, the inferred
scan segments and the user defined scan segments of the first scan chain
being of a first common clock domain; 2) automatically linking inferred
scan segments accessed in step a) with user defined scan segments accessed
in step b) to form the second scan chain, the inferred scan segments and
the user defined scan segments of the second scan chain being of a second
common clock domain, wherein the first and the second scan chain are
substantially balanced.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a data flow diagram illustrating the check test, specification,
reporting, analysis and synthesis processes of the hierarchical scan
system of the present invention.
FIG. 1B is a process flow diagram illustrating the check test,
specification, reporting, analysis and synthesis processes of the
hierarchical scan system of the present invention.
FIG. 1C illustrates an exemplary integrated circuit design.
FIG. 2A and FIG. 2B illustrate process steps performed within the analysis
process of the present invention for balancing of scan chains.
FIG. 2C illustrates process steps performed within the analysis process of
the present invention for scan chain balancing optimization.
FIG. 3A and FIG. 3B illustrate process steps performed within the analysis
process of the present invention for balancing segments among a set of
chains.
FIG. 4A illustrates pre-processing steps performed by the present invention
within the analysis process for identification of segments in preparation
for balancing.
FIG. 4B illustrates pre-processing steps called by the process of FIG. 4A
for analyzing a hierarchical design for scan structures therein.
FIG. 5 illustrates process steps within the synthesis process of the
present invention.
FIG. 6A and FIG. 6B illustrate an example input design database and an
example implemented scan structure for a single clock domain design with
two chains specified.
FIG. 7A and FIG. 7B illustrate an example input design database and an
example implemented scan structure for a mixed clock edge design.
FIG. 8A and FIG. 8B illustrate an example input design database and an
example implemented scan structure for a mixed clock edge design with edge
mixing allowed.
FIG. 9A and FIG. 9B illustrate an example input design database and an
example implemented scan structure for a multiple clock domain design.
FIG. 10A and FIG. 10B illustrate an example input design database and an
example implemented scan structure for a multiple clock domain design with
clock mixing and lock-up latches inserted.
FIG. 11A and FIG. 11B illustrate an example input design database having
three modules and a partial specification of scan ordering before scan
insertion.
FIG. 12A illustrates a design with a single clock domain with minimal scan
before scan insertion, FIG. 12B illustrates the scan insertion of the
design of FIG. 12A at the module level and FIG. 12C illustrates the scan
insertion of the design of FIG. 12A at the top level.
FIG. 13A and FIG. 13B illustrate an example input design database and an
example implemented scan structure for a single clock domain design with
two scan chains specified at the top level.
FIG. 14A and FIG. 14B illustrate an example input design database and an
example implemented scan structure for a single clock domain design with
the rebalance option set.
FIG. 15 is a block diagram of a computer aided design (CAD) system
implementing the scan processes of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
A system and method for providing design for test circuitry within a
integrated circuit (IC) design that can include hierarchical structured
subdesigns. In the following detailed description of the present
invention, numerous specific details are set forth in order to provide a
thorough understanding of the present invention. However, it will be
obvious to one skilled in the art that the present invention may be
practiced without these specific details. In other instances well known
methods, procedures, components, and circuits have not been described in
detail as not to unnecessarily obscure aspects of the present invention.
NOTATION AND NOMENCLATURE
Some portions of the detailed descriptions which follow are presented in
terms of procedures, logic blocks, processing, and other symbolic
representations of operations on data bits within a computer memory. These
descriptions and representations are the means used by those skilled in
the data processing arts to most effectively convey the substance of their
work to others skilled in the art. A procedure, logic block, process,
program, etc., is here, and generally, conceived to be a self-consistent
sequence of steps or instructions leading to a desired result. The steps
are those requiring physical manipulations of physical quantities. These
physical quantities represent actual, physical, artifacts. Usually, though
not necessarily, these quantities take the form of electrical or magnetic
signals capable of being stored, transferred, combined, compared, and
otherwise manipulated in a computer system. It has proven convenient at
times, principally for reasons of common usage, to refer to these signals
as bits, values, elements, symbols, characters, terms, numbers, or the
like.
It should be borne in mind, however, that all of these and similar terms
are to be associated with the appropriate physical quantities they
represent and are merely convenient labels applied to these quantities.
Unless specifically stated otherwise as apparent from the following
discussions, throughout the present invention, discussions utilizing terms
such as "processing" or "computing" or "calculating" or "determining" or
"displaying" or the like, refer to the action and processes of a computer
system, or similar electronic computing device, that manipulates and
transforms data represented as physical (electronic) quantities within the
computer system's registers and memories into other data similarly
represented as physical quantities within the computer system memories or
registers or other such information storage, transmission or display
devices. The physical quantities are themselves representative of actual,
physical, artifacts. For instance, within the present invention the
physical quantities are representative of logic gates and connections
fabricated on a semiconductor substrate to realize an integrated circuit.
COMPUTER AIDED DESIGN (CAD) COMPUTER SYSTEM
Refer to FIG. 15 which illustrates a computer aided design (CAD) system 112
implemented to execute processes of the present invention. In general,
computer system 112 used by the preferred embodiment of the present
invention comprise an address/data bus 100 for communicating address and
data information, one or more central processors 101 coupled with the bus
100 for processing information and instructions, a computer readable
volatile memory unit (e.g., random access memory, flash memory, etc.) 102
coupled with the bus 100 for storing information (e.g., design database
information) and instructions for the central processor 101, a computer
readable non-volatile memory unit (e.g., a read only memory) 103 coupled
with the bus 100 for storing static information and instructions for the
processor 101, a computer readable data storage device 104 such as a
magnetic or optical disk and disk drive coupled with the bus 100 for
storing information and instructions, and a display device 105 coupled to
the bus 100 for displaying information to the computer user. Optionally,
computer system 112 can also include an alphanumeric input device 106
(e.g., keyboard) including alphanumeric and function keys coupled to the
bus 100 for communicating information and command selections to the
central processor 101, a cursor control device 107 (e.g., mouse, trackpad,
pen and pad, trackball, etc.) coupled to the bus for communicating user
input information and command selections to the central processor 101, and
a signal generating device 108 coupled to the bus 100 for communicating
command selections to the processor 101.
It is appreciated that the processes of the present invention to be
described below (e.g., the processes of check test 220, specification 230,
reporting 240, analysis 250, and synthesis 260) are implemented, in one
embodiment of the present invention, as program code or instructions
stored within the above referenced computer readable memory units. Upon
execution of this code (or instructions) by the processor, the above
described processes cause computer system 112 to perform in the manner
indicated below.
HIERARCHICAL SCAN SYSTEM OF THE PRESENT INVENTION
I. Scan Test System 205
DATA INTERFACE. FIG. 1A illustrates the components of the scan test system
205 ("system 205") of the present invention. Five processes are shown:
check test 220, specification 230, reporting 240, analysis 250, and
synthesis 260 processes. Each of the above processes interact with a scan
chain design database 210 ("database 210") as shown in FIG. 1A. Database
210 defines a hierarchical structured integrated circuit (IC) design
having cells organized with a top level and one or more design modules
defined therein (e.g., see FIG. 11A with top level 740 and "child" modules
742, 744, and 746). The database 210 is a netlist of logic cells and
either contains or is specified to contain scan structure (e.g., scan
cells, scan segments, hierarchical cells, functional shift segments,
etc.). Individual modules within database 210 1) can contain no scan
structure at all, 2) can contain scan replaced sequential cells but not
routed sequential cells, 3) can contain fully scan replaced and routed
sequential cells, 4) can contain fully scan replaced sequential cells with
loopback connections, or 5) can contain any mixture of the above. The same
is true for sequential cells located within database 210's top level but
not located within any module. It is appreciated that the above five
processes can be made applicable to, or limited only to, any subdesign
(e.g., module) within database 210 by specifically naming the desired
module as the "current design" (e.g., using a current.sub.--
design=command) This facilitates bottom up scan structure architecting as
described further below.
The present invention system 205 provides a vehicle for automatic
architecting of complete scan chains (e.g., primary input to primary
output) within the IC design represented by database 210 and, during this
process, allows a user to define and utilize specialized scan structures
(e.g., a user defined scan segment) which can represent a subdesign (e.g.,
module) scan chain or other sequential structure, like a shift register.
In effect, the scan segments can be integrated with other scan structures
(e.g., using the set.sub.-- scan.sub.-- path command) to construct
complete scan chains. Those portions of a scan chain not specifically
identified by the user can be automatically supplemented by system 205
according to certain default behaviors.
The present invention system 205 also identifies certain inferred scan
structures (e.g., inferred scan segment) that exist within a module that
was either created by constraint driven scan insertion processes used by
the present invention or that was processed through check test process 220
of the present invention (a design rule checker). By providing the above
operations, the present invention system 205 allows the insertion of scan
structure within a hierarchical IC design. To this extent, scan structures
that exist within modules of the IC design can be used in the creation of
complete scan chains, rather than being destroyed and rerouted during
creation of the complete scan chain (as done in the past). As discussed in
detail below, a number of different specification commands are supported
for the above.
According to system 205, a check test process 220 is implemented to read
the contents of database 210 in order to perform specific well known
design rule checking processes. With respect to the design rule checking
processes, process 220 identifies existing scan structure within database
210 and analyzes any existing scan chains for scan rule violations via
symbolic simulation (e.g., token dropping and monitoring). Process 220
flags valid sequential cells for replacemen | | |
