Described are a method and device for tracking memory cell currents using a tracking memory cell circuit wherein the challenges resulting from current degradation and process variations are eliminated. A special strap cell is provided to eliminate ground bounce phase shifting. The tracking and strap cells along with the tracking scheme allow for better tracking of current within the array without the necessity of adding timing margin. The tracking memory cell circuit is a modified version of the memory cell used in the memory array and provides a reference current for the sense amplifier that is compared against the addressed memory cell. Tracking cells are placed in the center of the memory array making them nearer to the active memory cells. As a result, they better mirror the physical and electrical characteristics of the active memory cells over previous methods.

This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors. Form a first Vss strap/conductor in a first direction in a first one of the metallization layers. Form a second Vss strap/conductor in a second direction in a second one of the metallization layers. Form a VIA/contact between the conductive reference potential node and the first and second Vss strap/conductors.

An electronic device such as an integrated circuit includes a power distribution system having a plurality of symmetrical power distribution structures, for example as triplet power line structures, distributed in parallel and spaced evenly across the surface of the electronic device. A plurality of circuit blocks are coupled to receive power through the power distribution structures. Each of the power distribution structures comprises a first power line for providing a first power supply voltage, and a second power line and a third power line for providing a second supply voltage. The second power line and the third power line are disposed symmetrically on opposite sides of the first power line.

A power distribution system for a semiconductor die includes bonding pads located adjacent to and connected to power busses with connections between the bonding pads providing a parallel path for current. Connections may be provided by stitch bonds, by conductors within a substrate or by other means.