A phase lock loop circuit includes an oscillator, a digital mixer, a comparator, a loop amplifier, and a low-pass filter. The oscillator has an oscillation frequency controlled by a control voltage. The digital mixer is constituted by a digital element to output a difference frequency signal between an oscillation output from the oscillator and an input mixing signal. The comparator compares at least the phase of the difference frequency signal output from the digital mixer with that of a reference frequency signal, and outputs a difference signal. The loop amplifier and the low-pass filter generate the control voltage for the voltage controlled oscillator on the basis of the difference signal output from the comparator.
A transmitting device generates a modulation signal depending on data to be transmitted. The transmitting device includes a transmission frequency generation device that is controlled depending on the signal in order to produce a transmission frequency corresponding to the modulation signal. A calibration device is provided for automatically calibrating the amplitude of the modulation signal during the operation of the transmitting device. This eliminates time-consuming and therefore costly adjustment steps during the production of the transmitting device.
A method of controlling a frequency synthesizer and a frequency synthesizer having a controllable output signal frequency and including a direct digital synthesizer whose output signal is coupled to the input of a phase-locked loop. To reduce the settling time of the synthesizer, the direct digital synthesizer includes a control circuit for controlling the frequency of the direct digital synthesizer from a first frequency to a second frequency in accordance with predetermined frequency steps.
A phase-locked loop (PLL) includes a final mixer on its output. The final mixer subtracts out a noise or error term from the PLL's output to reduce noise and jitter. A first mixer generates the error term by subtracting a feedback clock from the reference clock. This error term is near D.C. since the feedback and reference clocks are at the same frequency. When this error term is subtracted from the PLL output, a secondary maxima in the noise plot at the PLL's loop bandwidth is removed. A feedback counter receives the output of the voltage-controlled oscillator (VCO) before the final mixer. Outer-band noise created by the VCO is subtracted out by the final mixer, using the error term generated by the first mixer. The mixers reduce noise generated by the VCO or from other sources in the PLL.
