High speed temporary package and interconnect for testing semiconductor dice and method of fabrication

What is claimed is:

1. A temporary package for testing a semiconductor die comprising:

a base adapted to retain the die, the base comprising a plurality of terminal contacts and an opening formed therein;

an interconnect placed through the opening and bonded to the base, the interconnect comprising a plurality of first contacts configured to establish temporary electrical communication with a plurality of second contacts on the die, and a plurality of conductors in electrical communication with the first contacts and with the terminal contacts.

2. The package as claimed in claim 1 wherein the die comprises an unpackaged die.

3. The package as claimed in claim 1 wherein the die comprises a chip scale package.

4. The package as claimed in claim 1 wherein the interconnect is bonded to the base by TAB bonding or wire bonding.

5. A temporary package for testing a semiconductor die comprising:

a base adapted to retain the die, the base comprising an opening and a plurality of terminal contacts and conductive traces in electrical communication with the terminal contacts;

an interconnect placed through the opening and bonded to the base, the interconnect comprising a plurality of first contacts configured to establish temporary electrical communication with a plurality of second contacts on the die; and

a tape comprising metal bumps bonded to the conductors on the interconnect and to the conductive traces on the base to establish electrical communication therebetween.

6. The package as claimed in claim 5 wherein the second contacts comprise second metal bumps and the first contacts comprise indentations sized to retain the second metal bumps.

7. The package as claimed in claim 5 wherein the second contacts comprise second metal bumps and the first contacts comprise indentations with projections configured to penetrate the second metal bumps.

8. A temporary package for testing a bare semiconductor die or a chip scale package comprising:

a base configured to retain the die or the chip scale package, the base comprising an opening, a plurality of terminal contacts connectable to test circuitry, and a plurality of conductive traces in electrical communication with the terminal contacts;

an interconnect placed through the opening and bonded to the base, the interconnect comprising a plurality of first contacts comprising indentations configured to retain and establish temporary electrical communication with a plurality of metal bumps on the die or on the chip scale package, the indentations comprising conductive layers in electrical communication with a plurality of conductors on the interconnect; and

a plurality of bonded connections between the conductive traces on the base and the conductors on the interconnect.

9. The package as claimed in claim 8 wherein the bonded connections comprise TAB tape.

10. The package as claimed in claim 8 wherein the indentations comprise penetrating projections configured to penetrate the metal bumps.

11. The package as claimed in claim 8 wherein the conductors comprise a plurality of connection pads for the bonded connections.

12. A temporary package for testing a chin scale package comprising:

a package base configured to retain the chip scale package, the base comprising an opening;

an interconnect placed through the opening and bonded to the base;

a first contact and a second contact on the interconnect, each contact comprising an indentation with a conductive layer thereon configured to retain and establish electrical communication with a metal bump on the chip scale package;

a first conductor on the interconnect located in a first plane in electrical communication with the first contact; and

a second conductor on the interconnect located in a second plane in electrical communication with the second contact.

13. The package as claimed in claim 12 wherein the conductive layer comprises a material selected from the group consisting of metal and metal silicide.

14. The package as claimed in claim 12 wherein the indentation includes a projection configured to penetrate into the metal bump.

15. The package as claimed in claim 12 wherein an electrical path between the package base and the first and second conductors comprises metal bumps formed on microbump tape.

16. The interconnect as claimed in claim 12 wherein the first conductor and the second conductor include metal connection pads arranged in an array along a periphery of the interconnect.

17. A system for testing a semiconductor die or a chip scale package comprising:

a temporary package for retaining the die or the chip scale package, the temporary package comprising a base including an opening therein and a plurality of terminal contacts in electrical communication with a plurality of conductive traces;

an interconnect placed through the opening and bonded to the base, the interconnect comprising a plurality of first contacts for establishing temporary electrical communication with a plurality of second contacts on the die or the chip scale package, and a plurality of conductors in electrical communication with the first contacts; and

a tape with metal bumps thereon, the metal bumps bonded to the conductors and to the conductive traces on the base.

18. The system as claimed in claim 17 further comprising a force applying mechanism for biasing the die or the chip scale package against the interconnect.

19. A method for testing a semiconductor die comprising:

providing a temporary package for the die comprising an opening, a plurality of terminal contacts, and a plurality of conductive traces in electrical communication with the terminal contacts;

providing an interconnect comprising a plurality of first contacts configured to make electrical contact with a plurality of second contacts on the die, the first contacts in electrical communication with conductors formed on the interconnect;

providing a tape with a plurality of metal bumps;

placing the interconnect through the opening;

bonding the metal bumps on the tape to the conductive traces and to the conductors to establish electrical communication therebetween; and

applying test signals through the terminal contacts, conductive traces, conductors and first contacts to the die.

20. The method as claimed in claim 19 wherein the second contacts comprise second metal bumps and the first contacts comprise indentations covered with conductive layers.

21. The method as claimed in claim 19 wherein the tape comprises TAB tape.

22. The method as claimed in claim 19 wherein the first contacts comprise penetrating projections for penetrating the second contacts.

23. The method as claimed in claim 19 wherein the second contacts comprise second metal bumps and the first contacts comprise indentations configured to retain the second metal bumps and penetrating projections configured to penetrate the second metal bumps.

24. A method for testing a chip scale package comprising:

providing a temporary package for packaging the chip scale package, the temporary package comprising an opening and a plurality of terminal contacts in electrical communication with a plurality of conductive traces;

providing an interconnect comprising a plurality of first contacts in electrical communication with a plurality of conductors, the first contacts comprising indentations with conductive layers thereon configured to retain and electrically engage bumped contacts on the chip scale package;

placing the interconnect through the opening and bonding the conductors to the conductive traces to establish electrical communication therebetween; and

assembling the chip scale package in the temporary package with the first contacts in electrical communication with the bumped contacts.

25. The method as claimed in claim 24 wherein bonding the conductors to the conductive traces comprises TAB bonding.

26. A method for fabricating a temporary package for testing a semiconductor die, comprising:

providing a base comprising an opening, a plurality of terminal contacts and a plurality of conductive traces in electrical communication with the terminal contacts;

providing an interconnect comprising a plurality of first contacts in electrical communication with a plurality of conductors, the first contacts configured to electrically engage second contacts on the die;

placing the interconnect through the opening; and

bonding the conductive traces to the conductors.

27. The method as claimed in claim 26 wherein bonding comprises TAB bonding.

28. The method as claimed in claim 26 wherein the first contacts comprise indentations and the second contacts comprise metal bumps.

29. The method as claimed in claim 26 wherein the die comprises a chip scale package.

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FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and more particularly to a high speed temporary package and interconnect for testing semiconductor dice, to a method for testing dice using the interconnect, and to a method for fabricating the interconnect.

BACKGROUND OF THE INVENTION

Semiconductor dice must be tested during the manufacturing process to evaluate various electrical parameters of the integrated circuits formed on the dice. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dice. Standard tests for gross functionality are typically performed by probe testing the dice at the wafer level using probe cards and wafer steppers. Burn-in testing is typically performed after the dice have been singulated and packaged using a burn-in oven or similar testing apparatus in electrical communication with test circuitry. Among the tests performed are dynamic burn-in, input/output leakage, speed verification, opens, shorts, refresh and a range of algorithms to verify AC parameters.

In the case of unpackaged dice, marketed by manufacturers as known good dice (KGD), temporary packages are required to house a single bare die for burn-in and other test procedures. This type of temporary package is described in U.S. Pat. Nos. 5,541,525, 5,519,332 and 5,495,179 to Wood et al.

These temporary packages typically include an interconnect component for establishing temporary electrical communication with the die. The interconnect can include a substrate with contact members for electrically contacting the bond pads or other contact locations on the die. The interconnect can also include conductors, such as metallized traces, for providing a conductive path from testing circuitry to the contact members. Interconnects for temporary packages are disclosed in U.S. Pat. Nos. 5,483,741 and 5,523,697 to Farnworth et al., incorporated herein by reference.

With advances in the architecture of semiconductor devices, it is advantageous to perform some testing of integrated circuits using very high speed testing signals. For example, testing frequencies of 500 MHz and greater are anticipated for some memory products such as DRAMS. The temporary packages and interconnects used to test dice must be capable of transmitting signals at these high speeds without generating parasitic inductance and cross coupling (i.e., "cross talk").

Parasitic inductance and cross coupling can arise in various electrical components of the temporary packages and in the electrical interface of the interconnect with the temporary package. This can adversely effect the test procedure by causing the power supply voltage to drop or modulate during the test procedure and by causing noise and spurious signals.

For example, the conductors on the interconnect are typically wire bonded to corresponding conductive traces and terminal contacts formed on the temporary package. Capacitive coupling can occur between adjacent conductors on the interconnect and between adjacent bond wires to the conductors. High speed switching of the voltage levels in the conductors and bond wires can result in corresponding inadvertent changes in the voltage levels on nearby conductors, or bond wires, resulting in logic errors.

The problems of parasitic inductance and cross coupling can be compounded by the large number of bond pads contained on later generations of semiconductor dice. A large number of bond pads requires a corresponding large number of contact members and conductors on the interconnect. Because of their high density, it can be difficult to locate and construct the contact members and conductors without forming parasitic inductors and initiating cross talk and interconductor noise.

Because of these and other problems, there is a need in the art for improved temporary packages and interconnects for testing semiconductor dice and improved high speed testing methods.

SUMMARY OF THE INVENTION

In accordance with the invention, an improved temporary package and interconnect for testing semiconductor dice are provided. The temporary package comprises a base for retaining a single bare die and a force applying member for biasing the die against the interconnect. The interconnect mounts to the base and includes dense arrays of contact members and multi level conductors in electrical communication with the contact members. Insulating layers can be formed between adjacent levels of conductors to prevent cross talk and capacitive coupling between the conductors. Additionally, if desired, the conductors can be embedded in separate insulating layers to provide electrical isolation in both horizontal and vertical directions.

An electrical path between the contact members on the interconnect and terminal contacts on the package base can be formed by microbump tape similar to multi layered TAB tape. The microbump tape can include patterns of metal traces with microbumps (metal balls) formed in vias through the tape and electrically connected to the traces. The conductors on the interconnect can be formed with connections pads having a metallurgy for bonding to the microbumps. The microbumps can be formed of a solder alloy to provide a low resistance electrical path to the conductors that permits high speed testing.

A system for testing the die includes the interconnect, the temporary package, the microbump tape, and a testing apparatus such as a burn in board, for retaining the temporary package in electrical communication with test circuitry.

The multi level construction of the interconnect helps to overcome space limitations and permits a large number of input/output paths to be formed for a dense array of contact members. This allows testing of dice having a large number of bond pads and allows test procedures with a large number of separate input/output paths. In addition, conductors and insulating stacks on the interconnect can be used to form micro strip, embedded micro strip, and strip line conductor configurations and to tailor the electrical properties of the interconnect for high speed testing with lower noise. Furthermore, with this type of multi layered construction, impedance can be controlled and the conductors can be formed with dense peripheral arrays of connection pads.

For fabricating the interconnect, the contact members can be formed as raised members by etching a substrate and then covering the raised members with a conductive layer formed of a metal (e.g., aluminum) or a metal silicide (e.g., TiSi.sub.2). The contact members can also include penetrating projections for penetrating contact locations on the dice to a limited penetration depth. Alternately the contact members can be formed as indentations covered with a conductive layer and configured to electrically connect to bumped contact locations (e.g., solder bumps). The multi level conductors can be formed on the substrate using a metallization process in which patterned metal layers are alternated with insulating layers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a temporary package and interconnect constructed in accordance with the invention for testing semiconductor dice;

FIG. 2 is a bottom view of the temporary package shown in FIG. 1 illustrating terminal contacts formed on the package in a dense grid array;

FIG. 3 is a cross sectional view of the temporary package taken along section line 3--3 of FIG. 2 illustrating a terminal contact on the package;

FIG. 4 is a cross sectional view of the temporary package taken along section line 4--4 of FIG. 2 illustrating the laminated construction of the package;

FIG. 5 is a schematic plan view of an interconnect constructed in accordance with the invention;

FIG. 6 is a schematic cross sectional view illustrating the interconnect during testing of a semiconductor die and the electrical path between the interconnect and the temporary package;

FIG. 6A is a schematic cross sectional view equivalent to FIG. 6 illustrating an alternate embodiment interconnect for testing bumped semiconductor dice;

FIG. 7 is an enlarged cross sectional view taken along section line 7--7 of FIG. 6 illustrating the electrical connection between a contact member on the interconnect and a flat contact location on the die;

FIG. 7A is an enlarged cross sectional view taken along section line 7A--7A of FIG. 6A illustrating the electrical connection between an alternate embodiment indentation contact member and a bumped contact location on a bumped die;

FIG. 7B is an enlarged cross sectional view equivalent to FIG. 7A of an alternate embodiment contact member for bumped dice;

FIG. 7C is an enlarged cross sectional view equivalent to FIG. 7A of an alternate embodiment indentation contact member for bumped dice;

FIG. 8 is an enlarged cross sectional view taken along section line 8--8 of FIG. 5 illustrating multi level conductors on the interconnect in electrical communication with selected contact members;

FIG. 8A is an enlarged cross sectional view equivalent to FIG. 8 but illustrating multi level conductors on an interconnect having indentation contact members;

FIG. 9A is a schematic perspective view of contact members on the interconnect and multi level conductors to the contact members;

FIG. 9B is a schematic cross sectional view taken along section line 9B--9B of FIG. 9A;

FIG. 10 is a schematic cross sectional view illustrating an alternate embodiment layout of multi level conductors for the contact members;

FIG. 11 is a schematic cross sectional view illustrating another alternate embodiment layout of multi level conductors;

FIG. 12 is a schematic perspective view illustrating another layout of multi level conductors wherein the conductors are electrically connected to one another;

FIG. 12A is a cross sectional view taken along section line 12A--12A of FIG. 12 illustrating the electrical connection between the conductors; and

FIG. 13 is a schematic view partially cut away illustrating multi level conductors on an interconnect constructed in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, an interconnect 10 and temporary package 12 constructed in accordance with the invention are shown assembled with a semiconductor die 14. The interconnect 10 and temporary package 12 form a system for testing the die 14.

The interconnect 10 can be removably mounted to a base 16 of the temporary package 12 and is configured to establish temporary electrical communication between the die 14 and terminal contacts 22 formed on the base 16. For testing the die 14, the terminal contacts 22 on the temporary package 12 can be placed in electrical communication with test circuitry 15 (FIG. 2). Following the test procedure, the die 14 can be removed from the package 12 and used as a known good die (KGD).

The semiconductor die 14 can be a bare die or a chip scale package. A bare die does not include a conventional plastic or ceramic package but can include flat or bumped bond pads. Chip scale packages typically include thin protective coatings formed of glass or other materials bonded to the face and backside of a bare die.

In addition to the base 16, the temporary package 12 includes a force applying mechanism 20. The force applying mechanism 20 secures the die 14 to the base 16 and presses the die 14 against the interconnect 10. The force applying mechanism 20 can include a pressure plate 18 and a spring 24. Openings 26, 28 in the spring 24 and pressure plate 18 allow the die 14 to be held by a vacuum tool during alignment and assembly of the package 12. Clips 30 can be formed on the force applying mechanism 20 and removably attach to corresponding openings 32 formed in the base 16.

Still referring to FIG. 1, the package base 16 can include patterns of conductive traces 34 in electrical communication with the terminal contacts 22. As will be further explained, electrical paths can be formed between the interconnect 10 and the conductive traces 34. In the illustrative embodiment the electrical paths are formed by microbump tape 36 (FIG. 6) bonded to the interconnect 10 and to the conductive traces 34 on the package base 16. Alternately the electrical paths can include wire bonds, or mechanical-electrical connectors such as clips or slide contacts.

As shown in FIGS. 3 and 4, the package base 16 can be formed of laminated ceramic layers 38a-38e. U.S. Pat. No. 5,519,332, incorporated herein by reference, describes a method for forming this type of package base 14. Briefly, this process involves forming metallized circuits in the x, y and z planes. These circuits are formed on green sheets of ceramic using a suitable metallization process and are interconnected with metal filled vias. The green sheets are then pressed together and sintered at high temperatures to form a unitary structure. Using this process the conductive traces 34 can be formed of suitable metals and interconnected to the terminal contacts 22.

The package base 16 can also be formed using a 3-D injection molding process out of a high temperature glass filled plastic or out of a glass filled resin laminate such as FR-4 board. Such a process is described in the previously cited U.S. Pat. No. 5,519,332. The package base 16 can also be formed using a Cerdip process in which a lead frame containing the conductive traces 34 or other electrical members is molded or laminated to a plastic or ceramic base material.

The conductive traces 34 on the package base 16 can also include land pads 40 (FIG. 3) wherein the terminal contacts 22 are formed. In FIG. 3 the land pads 40 are shown recessed into the package base 16. However, the land pads 40 can also be formed directly on an exterior surface of the package base 16. The land pads 40 can be formed out of a suitable metal or stack of metals. Exemplary metals can include gold, copper, silver, tungsten, tantalum, platinum, palladium and molybdenum or alloys of these metals. An exemplary stack can include a gold layer with nickel underplating. Other exemplary stacks can include other combinations of the above metals. A metallization process such as plating can be used to form the land pads 40. Such a plating process can include electrolytic or electroless deposition of a metal layer followed by resist coating, exposure, development, and selective wet chemical etching, if required.

The terminal contacts 22 can be formed on the land pads 40 as metal balls arranged in a dense grid pattern such as a ball grid array (BGA). The terminal contacts 22 can be configured for contact with a mating electrical connector such as a socket of a burn-in board in electrical communication with the test circuitry 15 (FIG. 2). One method for forming the terminal contacts 22 is by stencil printing a solder paste onto the land pads 34 followed by reflow into a spherical shape. U.S. patent application Ser. No. 08/584,628, now abandoned, incorporated herein by reference, discloses a method for forming a temporary package with land pads 40 and terminal contacts 22.

Referring to FIG. 5, the interconnect 10 is shown in greater detail. The interconnect 10 includes a substrate 44 formed of an etchable material such as silicon, germanium, silicon-on-glass or silicon-on-sapphire. The substrate 44 can also be formed of ceramic. In addition, the substrate 44 can be formed of a photosensitive glass, or glass-ceramic material, such as "FOTOFORM" manufactured by Corning.

The interconnect 10 includes arrays of contact members 46 configured to contact bond pads 48 (FIG. 6) or other contact locations on the die 14. The contact members 46 project from an active surface 11 of the interconnect 10. The active surface 11 can also be referred to as the "face" or "circuit side" of the interconnect 10.

In addition, the interconnect 10 includes patterns of multi level conductors 50 formed on or subjacent to the active surface 11 of the interconnect 10. As used herein, the term "multi level conductors" means that the conductors 50 are not co-planar to one another but are on different levels, layers or planes of the interconnect 10. Typically these different levels, layers or planes, are parallel to one another and to the major plane of the active surface 11 of the interconnect 10.

The multi leve