Inverted dielectric isolation process

Claims

What is claimed is:

1. A semiconductor structure comprising:

a semiconductor wafer having a doped element layer upon which a plurality of semiconductor devices are laterally arranged on a first surface of the semiconductor wafer, the semiconductor wafer having a second surface opposite to the first surface;

a thermally conductive bond layer forming a conformal bond with the first surface of the semiconductor wafer;

a dielectric layer coupling the first surface to the bond layer;

a support substrate coupled to the semiconductor wafer by the bond layer; and

a plurality of empty isolation trenches extending from the second surface substantially to the dielectric layer overlying the first surface and enclosing and mutually electrically isolating the plurality of semiconductor devices, the empty isolation trenches being formed into the semiconductor wafer to remove all inactive regions so that only active regions in the semiconductor devices remain.

2. A structure as in claim 1, further comprising:

a semiconductor device of the plurality of semiconductor devices including:

a plurality of ion diffusion regions extending vertically from the first surface a controlled depth toward the second surface; and

a heavily-doped diffusion region substantially uniformly diffused laterally and extending from the second surface toward the first surface a controlled depth;

an interconnect structure overlying the first surface and the dielectric layer, the dielectric layer having a first aperture and a second aperture overlying a selected diffusion region of the plurality of ion diffusion regions, the interconnect structure further including:

a patterned contact metallization layer formed on the first surface including a first metallization contact and a second metallization contact abutting and electrically coupling to the selected diffusion region through the second aperture; and

a conductor layer overlying the second surface and a sidewall surface of an isolation trench of the plurality of isolation trenches and forming an ohmic contact with the heavily-doped diffusion region on the second surface and electrically coupling to the first metallization contact at an intersection between the sidewall surface and first surface.

3. A structure as in claim 1, further comprising:

a transistor of the plurality of semiconductor devices including:

a frontside ion diffusion region selectively positioned laterally and extending laterally a selected width and extending vertically from the first surface toward the second surface a selected frontside diffusion depth; and

a backside doped region substantially uniformly doped laterally and extending vertically from the second surface toward the first surface a selected backside doping depth;

a patterned terminal contact coupling to the first surface;

a backside conductive layer formed on the second surface and coupling to the backside doped region; and

an isolation barrier bordering a sidewall surface of an isolation trench of the plurality of isolation trenches and extending from the backside conductive layer to the first surface; wherein the dielectric layer is a frontside dielectric layer formed between the patterned terminal contact and the first surface and having an aperture through which a metal via of the terminal contact electrically couples to the first surface.

4. A structure as in claim 3, wherein:

the isolation barrier includes:

a backside dielectric layer formed between the backside conductive layer and the second and sidewall surfaces in combination and having an aperture overlying the second surface;

the frontside dielectric layer is perforated by an aperture which extends from the first surface to the isolation trench;

the backside conductive layer is a metal layer formed overlying the second surface and the sidewall surface and overlapping the aperture in the frontside dielectric layer at an intersection of the first surface and the isolation trench, which couples the backside doped region to the patterned terminal contact on the first surface through the perforation in the frontside dielectric layer;

the transistor is a bipolar transistor circuit;

the backside doped region is a heavily-doped first-conductive-type collector region; and

the frontside ion diffusion region includes:

a lightly-doped first-conductive-type collector region extending from the first surface vertically to the heavily-doped first-conductive-type backside doped region and extending laterally to the isolation trench;

a second-conductive-type opposite the first-conductive-type base diffusion region extending vertically from the first surface into the lightly-doped first-conductive-type collector region and extending laterally to the isolation trench; and

an first-conductive-type emitter diffusion region contained within the second-conductive-type opposite the first-conductive-type base diffusion region.

5. A structure as in claim 1, wherein a semiconductor device of the plurality of semiconductor devices comprises:

a lightly doped region in the element layer;

a heavily doped buried region buried within the element layer and having the same doping type as the lightly doped region of the element layer;

an enhanced conductivity region extending from the first surface a controlled depth into the lightly doped region of the element layer and having the same conductivity type as the lightly doped region of the element layer; and

a metal layer overlying a surface of an isolation trench of the plurality of isolation trenches of the semiconductor device so that the metal layer furnishes an ohmic contact to the buried region.

6. A structure as in claim 1, wherein the plurality of semiconductor devices comprise:

a high voltage vertical bipolar device including a collector region having:

a first lightly doped first-conductive-type epitaxial layer coupled to the first surface of the semiconductor wafer;

a diffused heavily-doped first-conductive-type buried layer adjacent to and separated from the first surface of the semiconductive wafer by the first lightly doped first-conductive-type epitaxial layer; and

a second lightly doped first-conductive-type epitaxial layer adjacent to and separated from the first lightly doped first-conductive-type epitaxial layer by the heavily-doped first-conductive-type buried layer; and

a low voltage vertical bipolar device including a collector region having:

a first lightly doped first-conductive-type epitaxial layer adjacent to the first surface and extending a controlled depth into the element layer from the first surface;

a diffused heavily-doped first-conductive-type buried layer adjacent to the first lightly doped first-conductive-type epitaxial layer and extending a controlled depth beyond the first lightly doped first-conductive-type epitaxial layer into the element layer;

a second lightly doped first-conductive-type epitaxial layer adjacent to the diffused heavily-doped first-conductive-type buried layer and extending a controlled depth beyond the diffused heavily-doped first-conductive-type buried layer into the element layer; and

an enhanced first-conductive-type region which extends vertically from the first surface to overlap the heavily-doped first-conductive-type buried layer and partially overlap the second lightly doped first-conductive-type epitaxial layer; and

further comprising a metal layer overlying a surface of an isolation trench of the plurality of isolation trenches of the semiconductor device so that the metal layer furnishes an ohmic contact to the buried region.

7. A structure as in claim 1 further comprising:

a semiconductor device of the plurality of semiconductor devices having a four-layer PNPN structure, including:

a plurality of ion diffusion regions extending vertically from the first surface a controlled depth toward the second surface; and

a heavily-doped diffusion region substantially uniformly diffused laterally and extending from the second surface toward the first surface a controlled depth;

an interconnect structure overlying the first surface and the dielectric layer, the dielectric layer having an aperture overlying a selected diffusion region of the plurality of ion diffusion regions, the interconnect structure further including:

a patterned contact metallization layer formed on the first surface including a metallization contact abutting and electrically coupling to the selected diffusion region through the aperture; and

a patterned conductor layer overlying the second surface and forming an ohmic contact with the heavily-doped diffusion region on the second surface.

8. A structure as in claim 7 further comprising:

an anode metallization contact overlying and electrically coupling to the conductor layer.

9. A structure as in claim 8 further comprising:

an N.sup.- -ion doped collector region of the plurality of ion diffusion regions extending from the first surface substantially throughout the element layer;

a P-ion doped gate region of the plurality of ion diffusion regions extending from the first surface a controlled lateral width and vertical depth within the element layer;

a heavily doped N.sup.+ -ion emitter region of the plurality of ion diffusion regions extending from the first surface a controlled lateral width and vertical depth contained within the gate region;

and wherein:

the heavily-doped diffusion region is diffused with P.sup.+ ions; and

the patterned contact metallization layer includes:

a gate metallization contact coupled to the P-ion gate region; and

a cathode metallization contact coupled to the N.sup.+ -ion emitter region.

10. A structure as in claim 1, further comprising:

an insulated gate bipolar transistor (IGBT) element including:

a plurality of ion diffusion regions in a double-diffused MOS (DMOS) structure extending from the first surface toward the second surface, the DMOS structure having diffused ions of a first conductivity type and of a second conductivity type, the DMOS structure including a source diffusion inside of a body diffusion, the source diffusion being diffused of ions of the first conductivity type; and

a heavily-doped bipolar emitter diffusion region having diffused ions of a second conductivity type complementary to the diffused ions of the first conductivity type in the DMOS structure substantially uniformly diffused laterally and extending from the second surface toward the first surface;

an interconnect structure overlying the first surface and overlying the dielectric layer, the dielectric layer having an aperture overlying selected diffusions of the DMOS structure, the interconnect structure including:

a source metal layer coupled to selected diffusions of the DMOS structure; and

a polysilicon gate formed between the source metal layer and the first surface; and

a second surface conductor layer drain terminal coupled and making an ohmic contact to the second surface.

11. A structure as in claim 10, further comprising:

a second surface dielectric layer overlying the second surface and overlying a sidewall surface of an isolation trench of the plurality of isolation trenches and having an aperture, the isolation trench bordering the sidewall surface and extending from the second surface dielectric layer to the first surface, the second surface conductor layer drain terminal overlying the second surface of the second surface dielectric layer and being electrically coupled to the bipolar emitter region via the second surface dielectric layer aperture.

12. A structure as in claim 11 wherein the DMOS structure further comprises:

a lightly doped drain (LDD) region extending vertically substantially from the first surface to the bipolar emitter diffusion region and extending laterally to the isolation trench, the LDD region being doped of ions of the first conductivity type; and

a diffused heavily-doped body region having a diffusion of ions of a type complementary to the first conductivity type, the diffused body region extending vertically from the first surface toward the second surface and extending laterally a controlled width;

a self-aligned body region having a diffusion of ions of a type complementary to the first conductivity type, the self-aligned body region being self-aligned with the polysilicon gate and extending from the first surface partially into the diffused body region; and

a heavily-doped source region having a diffusion of ions of the first conductivity type, the source region being self-aligned with an edge of the polysilicon gate and extending from the first surface to a depth more shallow than the self-aligned body region.

13. A structure as in claim 12 further comprising:

a plurality of DMOS structures;

a plurality of polysilicon gates connected in a polysilicon gate mesh layer;

wherein the source metal layer couples to the source regions of the plurality of DMOS structures so that current is substantially uniformly distributed through the DMOS source regions and heat is dissipated.

14. A structure as in claim 1, wherein the element layer includes a vertical transistor and a vertical collector leadout adjacent to the vertical transistor, both the vertical transistor and the vertical collector leadout extending from the first surface to the second surface and both the vertical transistor and the vertical collector leadout having sidewall surfaces mutually isolated by an isolation barrier, the structure further including:

a plurality of frontside ion diffusion regions including

a collector region extending throughout the vertical transistor and the vertical collector readout;

a base region of a complementary conductivity type to the collector region and extending into the collector region vertically within the vertical transistor from the first surface a selected base diffusion depth and extending laterally substantially across the vertical transistor, the dielectric layer including a base aperture overlying the base region;

a heavily-doped emitter region of the same conductivity type as the collector region and extending into the base region a selected emitter diffusion depth that is smaller than the base diffusion depth so that the emitter region depth is enclosed within the base region, the emitter region extending to sidewall surfaces on three sides and being bounded on a fourth side by the base region, the dielectric layer including an emitter aperture overlying the emitter region; and

a heavily-doped collector readout region within the collector regions and having the same conductivity type as the collector region and extending into the vertical collector readout from the first surface a selected collector leadout diffusion depth, the dielectric layer including a collector aperture overlying the collector readout region;

a backside diffusion region including

a heavily-doped collector ohmic contact diffusion of the same conductivity type as the collector region extending laterally substantially across the vertical transistor and substantially across the vertical collector leadout; and

a patterned terminal contact including a plurality of metallization terminal contacts extending through the frontside dielectric layer apertures;

a backside conductive layer formed on the second surface and coupled to the backside diffusion region; and

an isolation barrier including a local area of oxidation (LOCOS) region isolation trench bordering the sidewall surfaces and extending from the backside conductive layer to the first surface.

15. A structure as in claim 1 wherein the element layer includes a vertical transistor and a vertical collector readout adjacent to the vertical transistor both the vertical transistor and the vertical collector readout extending from the first surface to the second surface and both the vertical transistor and the vertical collector readout having sidewall surfaces mutually isolated by an isolation barrier, the vertical collector readout including a metal plug extending laterally to bound the sidewall surfaces and extending vertically from the second surface to the first surface, the structure further including:

a plurality of frontside ion diffusion regions including

a collector region extending throughout the vertical transistor, the dielectric layer including a collector aperture overlying the collector region;

a base region of a complementary conductivity type to the collector region and extending into the collector region vertically within the vertical transistor from the first surface a selected base diffusion depth and extending laterally substantially across the vertical transistor, the dielectric layer including a base aperture overlying the base region; and

a heavily-doped emitter region of the same conductivity type as the collector region and extending into the base region a selected emitter diffusion depth that is smaller than the base diffusion depth so that the emitter region is enclosed within the base region, the dielectric layer including an emitter aperture overlying the emitter region; and

a backside diffusion region including

a heavily-doped collector ohmic contact diffusion of the same conductivity type as the collector region extending laterally substantially across the vertical transistor to the metal plug;

a patterned terminal contact including a plurality of metallization terminal contacts extending through the emitter, base, and collector apertures of the dielectric layer; and

a plurality of isolation barriers including a local area of oxidation (LOCOS) region isolation trench bordering the sidewall surfaces and extending from the backside conductive layer to the first surface.

16. A semiconductor structure comprising:

a support substrate;

a bond layer coupled to the support substrate;

a bond layer element interconnect structure coupled to the bond layer including:

a dielectric layer perforated by a plurality of contact openings; and

an interconnect metal layer coupled to the dielectric layer and formed between the dielectric layer and the bond layer;

a semiconductor element layer having a first surface coupled to the dielectric layer, the semiconductor element layer being electrically accessible to the interconnect metal layer via the contact openings, the semiconductor element layer having a second surface and further including:

a plurality of semiconductor devices formed from a plurality of p-type and n-type conductivity regions; and

a plurality of isolation structures isolating the plurality of semiconductor devices, the isolation structures including an isolation trench surrounding a semiconductor device of the plurality of semiconductor devices, the isolation trench being formed into the semiconductor element layer to remove all inactive regions so that only active regions in the semiconductor devices remain.

17. A structure according to claim 16 wherein the bond layer is constructed from materials having a high thermal conductivity.

18. A structure according to claim 16 wherein the bond layer is interrupted by a bond layer gap.

19. A structure according to claim 16, wherein the support substrate is interrupted by a through-hole or channel extending to the bond layer for circulating liquids or gases.

20. A structure according to claim 16, wherein the support substrate is constructed from materials having a high thermal conductivity.

21. A structure according to claim 16, wherein the support substrate is constructed from materials having a high electrical conductivity.

22. A structure according to claim 16, wherein the dielectric layer includes an ion barrier layer.

23. A structure according to claim 16, wherein the dielectric layer is constructed from materials having a high thermal conductivity.

24. A structure according to claim 16, further comprising a passivation layer formed between the interconnect metal layer and the bond layer.

25. A structure according to claim 24, wherein the passivation layer is penetrated by a passivation opening.

26. A structure according to claim 24, wherein the passivation layer is constructed from materials having a high thermal conductivity.

27. A structure according to claim 24, wherein:

the bond layer is constructed from materials having a high electrical conductivity.

28. A structure according to claim 27, wherein the bond layer having a high electrical conductivity forms ohmic contacts with the interconnect metal layer.

29. A structure according to claim 24, wherein:

the bond layer is constructed from materials having a high electrical conductivity; and

the passivation layer is penetrated by a plurality of passivation openings; and

the bond layer is connected in an ohmic contact to the support substrate.

30. A structure according to claim 24 further comprising a bond interface layer coating a bond layer surface adjacent to the element layer.

31. A structure according to claim 24 wherein:

the dielectric layer in the bond layer element interconnect structure coats a bond layer surface adjacent to the support substrate; and the

bond layer dielectric layer is constructed substantially from materials having a high thermal conductivity.

32. A structure according to claim 31 further comprising:

an aperture formed in the bond layer dielectric layer; and

the bond layer extending through the bond layer dielectric layer aperture to form an ohmic contact with the support substrate.

33. A structure according to claim 16 further comprising a bond interface layer coating a bond layer surface adjacent to the support substrate.

34. A structure according to claim 16 wherein the plurality of semiconductor devices formed from a plurality of p-type and n-type conductivity regions include conductivity regions selected from a group of regions including:

a conductivity region extending from the first surface vertically into the semiconductor element layer;

a conductivity region extending from the second surface vertically into the semiconductor element layer;

a conductivity region intersecting with the first surface;

a conductivity region intersecting with the second surface;

a conductivity region intersecting with an isolation structure of the plurality of isolation structures;

a conductivity region intersecting with the isolation trench; and

a conductivity region buried within the semiconductor element layer.

35. A structure according to claim 16 wherein the isolation trench is substantially filled with a dielectric material.

36. A structure according to claim 16 further comprising:

a dielectric layer coating the isolation trench; and

polysilicon filling the isolation trench.

37. A structure according to claim 16 further comprising:

a patterned conductor layer coupled to the second surface of the semiconductor element layer.

38. A structure according to claim 37 wherein:

the semiconductor element layer includes an ohmic region adjacent to the second surface; and

the patterned conductor layer forms an ohmic contact with the ohmic region.

39. A structure according to claim 37 wherein the patterned conductor layer forms a schottky contact with the second surface.

40. A structure according to claim 37 wherein the patterned conductor layer forms a bond pad for attachment of a bond wire.

41. A structure according to claim 37 wherein the patterned conductor layer extends along a sidewall surface of the isolation trench to a trench foot surface adjacent to the first surface of the semiconductor element layer.

42. A structure according to claim 41 wherein the patterned conductor layer forms an ohmic contact with an ohmic region formed in a vicinity of an intersection of the first surface and the sidewall surface.

43. A structure according to claim 41 wherein the patterned conductor layer forms an ohmic contact with an ohmic region formed in a buried layer in a vicinity of the sidewall surface.

44. A structure according to claim 41 wherein:

the dielectric layer of the bond layer element interconnect structure is perforated by a contact opening adjacent to the trench foot surface; and

the patterned conductor layer further extends over the trench foot surface through the contact opening adjacent to the trench foot surface and contacts the interconnect metal layer at a via contact.

45. A structure according to claim 16 further comprising:

a second surface dielectric layer coupled to the second surface of the semiconductor element layer and a sidewall surface of the isolation trench;

the second surface dielectric layer being penetrated by an aperture at a selected location.

46. A structure according to claim 45, wherein the second surface dielectric layer includes an ion barrier layer.

47. A structure according to claim 45 further comprising:

a patterned conductor layer coupled to the second surface dielectric layer; wherein the patterned conductor layer extends through the aperture in the second surface dielectric layer to the second surface of the semiconductor element layer.

48. A structure according to claim 45 further comprising:

a patterned conductor layer coupled to the second surface dielectric layer; wherein the patterned conductor layer extends along the sidewall surface of the empty isolation trench through the aperture in the second surface dielectric layer and connects to the interconnect metal layer.

49. A structure according to claim 45, wherein the aperture in the second surface dielectric layer provides a bonding pad access to the second surface.

50. A structure according to claim 45, wherein the aperture in the second surface dielectric layer provides a bonding pad access to the first surface.

51. A structure according to claim 45, wherein the second surface dielectric layer is a planarizing dielectric layer that forms a planarized surface substantially parallel to the second surface.

52. A structure according to claim 16 further comprising:

a second surface patterned conductor layer coupled to the second surface of the semiconductor element layer;

a second surface dielectric layer coupled to the second surface patterned conductor layer, the second surface dielectric layer being penetrated by an aperture at a selected location; and

a second surface patterned interconnect layer coupled to the second surface dielectric layer and extending through the aperture to form an electrical contact with the second surface patterned conductor layer.

53. A structure according to claim 52 further comprising:

a second surface passivation layer coupled to the second surface patterned interconnect layer, the second surface passivation layer being penetrated by an aperture at a selected location.

54. A structure according to claim 53 wherein the aperture in the second surface passivation layer provides a bonding pad access to the second surface.

55. A structure according to claim 53, wherein the aperture in the second surface passivation layer provides a bonding pad access to the first surface.

56. A structure according to claim 16, further comprising a second surface conductor layer coupled to the second surface, wherein the a conductivity region of the plurality of p-type and n-type conductivity regions forms a low resistance second surface conductor layer leadout.

57. A structure according to claim 16, wherein the plurality of p-type and n-type conductivity regions form semiconductor devices of the plurality of semiconductor devices including complementary vertical NPN and PNP transistors.

58. A structure according to claim 16, wherein the plurality of p-type and n-type conductivity regions form semiconductor devices of the plurality of semiconductor devices including complementary vertical N-channel and P-channel transistors.

59. A structure according to claim 16, wherein the plurality of p-type and n-type conductivity regions form semiconductor devices of the plurality of semiconductor devices including a vertical IGBT transistor.

60. A structure according to claim 16, wherein the plurality of p-type and n-type conductivity regions form semiconductor devices of the plurality of semiconductor devices including a silicon-controlled rectifier (SCR).

61. A structure according to claim 16, wherein the plurality of p-type and n-type conductivity regions form semiconductor devices of the plurality of semiconductor devices including a vertical low-voltage device and a vertical high-voltage device compatibly isolated from the vertical low-voltage device.

62. A structure according to claim 16, wherein the plurality of isolation structures isolate semiconductor devices of the a plurality of semiconductor devices including a LOCOS-isolated verti