The analog-to-digital converting circuit apparatus of the invention is intended to realize both low voltage operation and high speed operation of an analog-to-digital converting circuit without impairing the precision characteristic. In plural boosting circuits, voltages higher than each supply voltage are generated. These plural boosting circuits are controlled as the control timing is sequentially shifted by the controller. The boosted voltages delivered from the plural boosting circuits are accumulated in the capacitor, and supplied into the analog-to-digital converter. In the analog-to-digital converter, at the timing other than the changeover timing of the converting action of the analog-to-digital converter, the plural boosting circuits are changed over sequentially, and the boosted voltages are converted from analog to digital values.

A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.

A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.

A technique for supplying drive voltage to the gate of a high-side depletion-mode N-channel MOS-device for high-side switches or any circuit with a depletion-mode N-channel MOS-device with its source at a voltage above local ground.

A new level shifting circuit, using a zero threshold voltage device, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has input connected to the input of the level shifting circuit and output forming an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first zero threshold NMOS transistor has the gate connected to a low bias voltage and the source connected to the first NMOS transistor drain. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first zero threshold NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input and the source connected to ground. A second zero threshold NMOS transistor has the gate connected to the low bias voltage, the source connected to the second NMOS transistor drain, and the drain connected to the level shifting output. A second PMOS transistor has the gate connected to the first zero threshold NMOS transistor drain, the source connected to the high supply, and the drain connected to the level shifting output.