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Description  |
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TECHNICAL FIELD
The present invention relates to integrated circuit devices, and more
particularly, to generation of differential signals in integrated circuit
devices.
BACKGROUND OF THE INVENTION
Integrated circuit devices often receive single-ended clock signals, i.e.,
signals that vary between a low voltage and a high voltage and are
referenced to a fixed reference voltage, typically either the low voltage
or the high voltage. Such circuit devices then respond to whether the
single-ended signal is above, below or equal to the reference voltage.
However, for proper operation some circuits require differential input
signals at a pair of terminals, i e., signals that vary in opposed
fashion. Such circuits then respond to whether the first terminal is at a
higher voltage than the second, or vice versa.
For example, delay stages in many delay-locked loops require high-speed,
low-skew differential inputs for proper operation. Additionally, phase
comparators in such delay-locked loops may also utilize differential input
signals. Because integrated circuit devices that include such delay-locked
loops often receive only single-ended signals, the single-ended signals
often must be converted to differential signals.
One approach to converting a single-ended signal into a differential signal
is shown in FIG. 1 where a single-ended signal CK is input to an inverter
40 to produce an inverted signal CK*. The noninverted and inverted signals
CK, CK* are then output at a pair of terminals 42, 44 as a differential
signal.
One problem with the above-described approach is that the output of the
inverter 40 (i.e., the inverted signal CK*) is delayed relative to the
input to he inverter 40 (the noninverted signal CK) by the response time
of the inverter 40. As a consequence, the differential signals CK, CK* are
"skewed," as shown in FIG. 2. One consequence of skew is that the signals
CK, CK* do not cross the midpoint V.sub.MID at the same times. Instead,
the midpoint crossings are offset by a skew time T.sub.d, which is
typically on the order of 50 picoseconds or more, even with a very fast
inverter 40. Such skew times are unacceptable for some applications, such
as very low jitter delaylocked loops and phase-locked loops. In such
circuits, skewed input signals can cause instability, drift and jitter in
the output signals. Consequently, it is desirable to produce differential
signals from single-ended signals with lowered skew times.
SUMMARY OF THE INVENTION
A low-skew single-ended-to-differential signal converter is driven by a
single-ended signal. The converter includes an inverter that produces an
inverted version of the single-ended signal. The inverted and noninverted
signals form a differential signal with a skew approximately equal to the
response time of the inverter. The skewed inverted and noninverted signals
drive output drivers that produce differential output signals with reduced
skew as compared to the inverted and noninverted versions of the
single-ended signal.
In one embodiment, the inverted signal drives a first input of a first
output driver and a third input of a second output driver. The noninverted
signal drives a second input of the first output driver and a fourth input
of the second output driver. Output terminals of the first and second
output drivers provide the differential signals.
The first output driver includes a first transfer gate formed by a
complementary transistor pair coupled between a supply voltage and a first
node. The first output driver also includes a second transfer gate formed
from a second complementary transistor pair coupled between a reference
voltage and the first node. The noninverted signal drives an NMOS
transistor in the second transfer gate and a PMOS transistor switch in the
first transfer gate. The inverted signal drives an NMOS transistor in the
first transfer gate and a PMOS transistor in the second transfer gate.
Initially, the noninverted signal is low and the inverted signal is high.
Under these conditions, the transistors in the first transfer gate are ON
and the transistors in the second transfer gate are OFF. The first node
voltage is thus high. A first output inverter coupled to the node outputs
a low output signal in response.
The noninverted signal transitions from low to high first. In response to
the transitioning noninverted signal the voltage at the first node begins
dropping toward a voltage determined by the resistances of the two ON
transistors. The node voltage does not fall below the threshold voltage of
the first output inverter and the output of the first driver circuit
remains low.
The inverted signal transitions low slightly after the noninverted signal
transitions high and the first node voltage drops to the reference
voltage. The first output inverter produces a high-going output signal in
response.
The second output driver includes a third transfer gate formed from third
complementary transistor pair and a fourth transfer gate formed from a
fourth complementary transistor pair. The third transfer gate is coupled
between a second node and a supply voltage and the fourth transfer gate is
coupled between the reference voltage and the second node. However,
connections to the third and fourth transfer gates are inverted relative
to the connections to the first and second transfer gates so that the
second node voltage is initially high. A second output inverter coupled to
the second node produces a low output signal in response.
When the noninverted signal transitions high, the NMOS transistor in the
third transfer gate turns ON and the PMOS transistor in the fourth
transfer gate turns OFF raising the second node voltage. The second node
voltage does not rise high enough to trigger the second output inverter,
so the second output voltage remains low.
When the inverted signal transitions low, the second node voltage is pulled
fully low and the second output signal goes high. Because transitions of
the differential signal and the complementary differential signal are both
activated by transitions of the same signal (the inverted signal), skew of
the differential signals is reduced relative to skew of the inverted and
noninverted signals.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of a prior art single-ended-to-differential signal
converter.
FIG. 2 is a signal timing diagram showing skewed outputs of the circuit of
FIG. 1.
FIG. 3 is a schematic of a single-ended-to-differential signal converter
according to one embodiment of the invention.
FIG. 4 is a signal timing diagram showing inverted and noninverted signals,
node voltages and output voltages in the converter of FIG. 3.
FIG. 5A is an equivalent circuit diagram of the first output driver in the
single-ended-to-differential signal converter of FIG. 3 at time t.sub.0.
FIG. 5B is an equivalent circuit diagram of the first output driver in the
single-ended-to-differential signal converter of FIG. 3 at time t.sub.1.
FIG. 6A is an equivalent circuit diagram of the second output driver of the
single-ended-to-differential signal converter of FIG. 3 at time t.sub.0.
FIG. 6B is an equivalent circuit diagram of the second output driver of the
single-ended-to-differential signal converter of FIG. 3 at time t.sub.1.
FIG. 7 is a block diagram of a memory system including a memory device that
includes the converter of FIG. 3.
FIG. 8 is a block diagram of a computer system that includes the memory
system of FIG. 7.
DETAILED DESCRIPTION OF THE INVENTION
As shown in FIG. 3, a single-ended-to-differential signal converter 50
includes the inverter 40 of FIG. 1 and first and second driver circuits
52, 54 having respective noninverted inputs 56, 62 and inverted inputs 60,
58. The noninverted inputs 56, 62 are driven by the single-ended signal CK
and the inverted inputs 60, 58 are driven by the inverted signal CK*.
Each of the driver circuits 52, 54 includes two transfer gates 64, 66, 68,
70. The outputs of the transfer gates 64, 66 in the first driver circuit
52 are connected to a first node 72 and the outputs of the transfer gates
68, 70 in the second driver 54 are connected to a second node 74. A signal
input of the first transfer gate 64, 68 in each driver circuit 52, 54
receives a supply voltage V.sub.CC so that the first transfer gate 64, 68
in each driver circuit 52, 54 can couple the respective node 72, 74 to
V.sub.CC. The signal input of the second transfer gate 66, 70 in each
driver circuit 52, 54 receives the reference voltage V.sub.SS so that the
second transfer gate 66, 70 can couple the respective node 72, 74 to
V.sub.SS.
Each transfer gate 64, 66, 68, 70 includes an NMOS transistor 76, 78, 80,
90 coupled in parallel with a respective PMOS transistor 82, 84, 86, 88.
The gates of the transistors 78, 80, 82, 84 are connected to the input of
the inverter 40 so that the noninverted signal CK controls the transistors
78, 80, 82, 84. The gates of the transistors 76, 86, 88, 90 are connected
to the output of the inverter 40 such that the inverted signal CK*
controls the transistors 76, 86, 88, 90.
The operation of the converter 50 of FIG. 3 will now be explained with
reference to FIGS. 3, 4, 5A-B, and 6A-B. As shown in FIG. 4, at time
t.sub.0, the noninverted signal CK is low and thus holds the transistors
82, 84 ON and the transistors 78, 80 OFF. The inverted signal CK* is high
and holds the transistors 76, 90 ON and the transistors 86, 88 OFF. Thus,
at time t.sub.0, the first output driver circuit 52 can be represented by
the circuit equivalent shown in FIG. 5A where the OFF transistors 80, 88
are represented as open switches and the ON transistors 76, 84 are
represented as closed switches. As shown in the third graph of FIG. 4, the
voltage V.sub.NODEA of the first node 72 will equal the supply voltage
V.sub.CC. The high voltage V.sub.NODEA is inverted by an inverter 100 so
that the output voltage V.sub.01 is equal to the reference voltage
V.sub.SS at time to as shown in the fifth graph of FIG. 4. At time
t.sub.0, the second driver circuit 54 can be represented by the circuit
equivalent of FIG. 6A where the OFF transistors 78, 86 are represented as
open switches and the ON transistors 82, 90 are represented as closed
switches. The voltage V.sub.NODEB of the second node 74 will be held to
the reference voltage V.sub.SS, as shown in the fourth graph of FIG. 4.
The voltage V.sub.NODEB is inverted by an inverter 102 so that the output
voltage V.sub.02 will equal the supply voltage V.sub.CC as shown in the
sixth graph of FIG. 4.
At time t.sub.1, the noninverted signal CK transitions from low to high,
turning ON the transistors 78, 80 and turning OFF the transistors 82, 84.
The inverted signal CK* lags the noninverted signal CK by the skew time
T.sub.d. A signal transition of the noninverted signal CK from low to high
that begins at time t.sub.1, does not produce a corresponding transition
of the inverted signal CK* from high to low until time t.sub.2 (t.sub.1
+T.sub.d). Thus, the states of the transistors 76, 86, 88, 90 controlled
by CK* do not change at time t.sub.1.
Between times t.sub.1 and t.sub.2, the first driver circuit 52 can be
represented as shown in FIG. 5B and the second driver 54 can be
represented as shown in FIG. 6B, where the OFF transistors 82, 84, 86, 88
are removed for clarity. Considering only the first driver circuit 52 as
represented by the equivalent circuit of FIG. 5B, the ON NMOS transistors
76, 80 establish the voltage V.sub.NODEA of the node 72 at a voltage
V.sub.1 as shown in the third graph of FIG. 4. The voltage V.sub.1 is
shown closer to the supply voltage V.sub.CC than the reference voltage
V.sub.SS, as will now be explained with reference to FIG. 5B.
When the noninverted signal CK transitions high, the gates of the
transistors 76, 80 are coupled to the supply voltage V.sub.CC. The gate to
source voltage of the transistor 80 is equal to the difference between
V.sub.CC and V.sub.SS. Therefore, the transistor 80 turns ON and begins to
pull the node voltage V.sub.NODEA down. The transistor 76 begins to
conduct when the node voltage V.sub.NODEA becomes sufficiently low that
the gate to source voltage of the transistor 76 exceeds the transistor's
threshold voltage V.sub.TN. If the gate voltages and other conditions
remained constant, the node voltage V.sub.NODEA would eventually settle at
a voltage determined by the channel resistances of the transistors 76, 80.
In the preferred embodiment, the transistor 80 is selected with a higher
channel resistance than the transistor 76. Therefore, the node voltage
V.sub.NODEA remains above a threshold voltage V.sub.TI of the inverter 100
in response to the transition of the noninverted signal CK. The output
voltage V.sub.01 thus does not transition in response to the transitioning
noninverted signal CK at time t.sub.1.
The response of the second driver circuit 54 at time t.sub.1 is similar to
the response of the first driver circuit 52. As noted above, when the
noninverted signal CK transitions high, the transistor 78 turns ON and the
transistor 82 turns OFF. The ON transistors 78, 90 form a voltage divider
as shown in FIG. 6B. In the second driver circuit 54, the channel
resistances of the transistors 78, 90 are selected such that the node
voltage V.sub.NODEB rises less than halfway to V.sub.CC (i.e., below
V.sub.TI), as shown in the fourth graph of FIG. 4. Because the node
voltage V.sub.NODEB remains below the threshold voltage V.sub.TI of the
inverter 102, the output voltage V.sub.02 remains high.
At time t.sub.2, the inverted signal CK* transitions from high to low.
The transitioning inverted signal CK* turns OFF the transistors 76, 90 and
turns ON the transistors 86, 88. In the first driver circuit 52, both
transistors 76, 84 in the first transfer gate 64 are thus OFF and both
transistors 80, 88 in the second transfer gate 66 are ON. Thus, the node
voltage V.sub.NODEA is pulled below the threshold voltage V.sub.TI of the
inverter 100 at time t.sub.2 and the output voltage V.sub.01 transitions
high at time t.sub.3, which is slightly after time t.sub.2 due to the
delay of the inverter 100.
Referring to the second driver circuit 54, when the transitioning inverted
signal CK* turns ON the transistor 86 and turns OFF the transistor 90,
both transistors 78, 86 in the first transfer gate 68 of the second driver
54 are ON and both transistors 90, 82 in the second transfer gate 70 are
OFF. Therefore, the node voltage V.sub.NODEB rises to V.sub.CC at time
t.sub.2. As shown in the, sixth graph of FIG. 4, the inverter 102 responds
by sending the output voltage V.sub.02 low at time t.sub.3, which is
slightly after time t.sub.2 due to the delay of the inverter 102. Because
both of the output signals V.sub.01, V.sub.02 transition in response to
the transition of the inverted signal CK*, both output signals V.sub.01,
V.sub.02 transition at time t.sub.3. Skew between the output signals
V.sub.01, V.sub.02 is thus reduced relative to the inverted and
noninverted signals CK*, CK.
At time t.sub.4, the noninverted signal CK transitions from high to low,
tuning OFF the transistors 80, 78 and turning ON the transistors 84, 82.
In the first driver circuit, the ON PMOS transistors 84, 88 form a voltage
divider between the supply voltage V.sub.CC and the reference voltage
V.sub.SS. The transistor 88 is selected with a lower channel resistance
than the transistor 84, so that the node voltage V.sub.NODEA does not rise
above the threshold voltage V.sub.TI of the inverter 100. Therefore, the
inverter 100 does not produce a transition at time t.sub.4.
In the second driver circuit 54, the ON PMOS transistors 82, 86 form a
voltage divider between V.sub.CC and V.sub.SS and the node voltage
V.sub.NODEB falls. The transistor 82 is selected with a higher channel
resistance than the transistor 86. Therefore, the voltage V.sub.NODEB
remains above the threshold voltage V.sub.TI of he inverter 102 and the
output voltage V.sub.02 remains low at time t.sub.4.
When the inverted signal CK* transitions from low to high at time t.sub.5,
the transistors 76, 90 turn ON and the transistors 86, 88 turn OFF. The
first node 72 is thus coupled to V.sub.CC and the second node 74 is
coupled to V.sub.SS. As the node voltage V.sub.NODEA rises, it triggers
the output inverter 100 and the output voltage V.sub.01 returns low at
time t.sub.6, which is slightly after time t.sub.5 due to delay of the
inverter 100. Similarly, the second node is coupled to V.sub.SS by the ON
transistors 82, 90, pulling down the second node voltage V.sub.NODEB. The
falling node voltage V.sub.NODEB triggers the inverter 102 at time t.sub.5
and the output voltage V.sub.02 goes high at time t.sub.6.
The exemplary embodiment above employs transistors 76, 78, 80, 82, 84, 86,
88, 90 that have channel resistances selected to delay triggering the
output inverters 100, 102 until the inverted signal CK* transitions.
However, one skilled in the art will recognize that, at high frequencies,
the driver circuits 52, 54 will reduce skew even if the transistors 76,
78, 80, 82, 84, 86, 88, 90 in each voltage divider have equal channel
resistances. This can be seen by considering the capacitive loading of the
inverters 100, 102, represented as discrete capacitors 108, 110 in the
equivalent circuits of FIGS. 5A-B, 6A-B.
Returning to time t.sub.1, when the transistors 78, 80 turn ON and the
transistors 82, 84 turn OFF, the node voltage V.sub.NODEA does not
immediately change, due to the capacitor 108. Instead, the node voltage
V.sub.NODEA falls exponentially as the capacitor 108 discharges charges
through the channel resistance of the transistor 80 (and some of the
charge is replaced through the channel resistance of the transistor 76).
Thus, the node voltage V.sub.NODEA would not immediately trigger the
output inverter 100 at time t.sub.1, even if the channel resistances were
equal. The output transition will be therefore delayed toward time
t.sub.2. Similarly, the capacitor 110 slows development of the voltage
V.sub.NODEB at the second node 74, thereby delaying response of the
inverter 102 toward time t.sub.2.
At time t.sub.2, the node voltages VNODEA, V.sub.NODEB are quickly pulled
high and low respectively by the ON transistors 80, 88, 78, 86, ensuring
triggering of the inverters 100, 102 at or very shortly after time
t.sub.2. Thus, even if the channel resistances of the transistors 76, 78,
80, 82, 84, 86, 88, 90 were equal, the output signals V.sub.01, V.sub.02
would transition very close to time t.sub.3. Consequently, the signal
converter 50 improves skew even for equal channel resistances.
As shown in FIG. 7, a memory system 152 includes a memory device 158
containing the converter 50 that operates under control of a memory
controller 153. The memory controller 153 controls the memory device 158
through control data CD1-CDN and a single-ended reference clock signal
CCLKREF, carried by a control data bus 154 and a clock bus 155,
respectively. The memory controller 153 provides data DA1-DAM to the
memory device 158, synchronously with a data clock signal DCLKREF over a
data bus 156 and a data clock bus 157, respectively.
The memory device 158 includes a latching circuit 160 that operates under
control of a logic control circuit 161. The latching circuit 160 is formed
from a delay-locked loop 162 and control data latches 166. The control
data latches 166 receive control data CD1-CDN from the control data bus
154 and data latches 168 receive data DA1-DAM from the data bus 156.
Additionally, the latching circuit 160 receives the reference control
clock signal CCLKREF and the reference data clock signal DCLKREF from the
respective clock buses 155, 157.
The reference control clock signal CCLKREF is a single-ended continuous
clock signal that drives the delay-locked loop 162 at a frequency
f.sub.CCLK. The delay-locked loop 162 is formed from a variable delay
circuit 140, a comparator 146, and an integrator 148. The variable delay
circuit 140 is formed from the converter 50 of FIG. 3 and a multitap
variable delay line 170. The converter 50 converts the single-ended
reference control clock signal CCLKREF to a differential signal for use by
the delay line 170. The delay line 170 delays the differential reference
control clock signal CCLKREF, thereby providing several delayed clock
signals CCLK1-CCLKN, each at the frequency f.sub.CCLK and each delayed by
a respective time delay relative to the reference control clock signal
CCLKREF to form a delayed reference clock signal CCLKD. The delayed
reference clock signal CCLKD activates control data latches 166, thereby
latching control data CD1-CDN. The latched control data CD1-CDN is then
made available to the logic control circuit 161.
FIG. 8 is a block diagram of a computer system 200 that contains the memory
system 152 of FIG. 7. The computer system 200 includes a processor 202 for
performing computer finctions such as executing software to perform
desired calculations and tasks. The processor 202 also includes command,
address and data buses 210 to activate the memory system 152. One or more
input devices 204, such as a keypad or a mouse, are coupled to the
processor 202 and allow an operator to manually input data thereto. One or
more output devices 206 are coupled to the processor 202 to display or
otherwise input data generated by the processor 202. Examples of output
devices include a printer and a video display unit. One or more data
storage devices 208 are coupled to the processor to store data on or
retrieve data from external storage media (not shown). Examples of storage
devices 208 and storage media include drives that accept hard and floppy
disks, tape cassettes and compact-disc read-only memories.
From the foregoing it will be appreciated that, although specific
embodiments of the invention have been described herein for purposes of
illustration, various modifications may be made without deviating from the
spirit and scope of the invention. Accordingly, the invention is not
limited except as by the appended claims.
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