In a control block design methodology, control block design proceeds without the inclusion of scan functionality until the functional design specifications are met. After meeting the functional design specifications, a scan insertion tool is executed to automatically insert scan functionality. The insertion is performed in such a manner that the functional cells within the control block are not perturbed. Therefore, functional timing may be minimally affected, if at all. In one embodiment, a scan enable buffer is inserted at the end of each row in the control block. Flops (or other scannable storage devices) within the row are connected to the scan enable line provided by the scan enable buffer within the row. Additionally, flops are connected into a scan chain on a row-by-row basis, minimizing the length of the wires connecting the scan chain. If a particular scan chain wire exceeds a length which will meet scan timing requirements, a scan chain buffer can be inserted as well (e.g. at the end of the row).

An input/output characterization register is provided for characterizing an integrated circuit input or output. The register includes a normal data input, a characterization data input, and a data latch having a latch control input, a latch data input and a latch data output. The normal data input and the characterization data input are multiplexed with the latch data output to the latch data input.

A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry includes a scan chain in the form of a serial linkage between memory elements within a circuit, thereby allowing a test input to be serially shifted into the memory elements. The system operates by receiving a test disable signal at the circuit. In response to the test disable signal, the system moves the circuit into a test disable mode, which limits any damaging effects to the circuit caused by shifting the test input into the memory elements in the scan chain. Next, the system shifts the test input into the memory elements in the scan chain. T he system also determines whether the test input will cause damage to the circuit after the test input is completely shifted into the scan chain. If so, the system holds the circuit in the test disable mode so that the test input cannot damage the circuit. If not, the system moves the circuit out of test disable mode, and runs the circuit for at least one clock cycle in order to test the circuit.

An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.

A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.