The present invention provides an interpreter with reduced memory access and improved jump-through-register handling. In one embodiment, a method includes storing a handler for a bytecode in a cell of a predetermined size of a table, and generating an address of the handler for the bytecode using a shift and an ADD operation. In particular, the handler address is generated by adding a base address of the table and an offset into the table. In another embodiment, a method includes prefetching a target handler address for providing improved jump-through-register handling.

The invention relates to a matrix of memory cells for a semiconductor integrated microcontroller. The matrix is of the type intended for accommodation between macrocells of the microcontroller so as to reduce the needed circuit area on the semiconductor. The matrix comprises memory cells which are organized into rows and columns, with the number of columns defining the matrix height. The matrix height is advantageously variable according to the number of bits intended for selecting the matrix column, while its width is dependent on the overall capacity of the memory.

A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

The present invention allows the frame buffer to be dynamically reconfigurable during the processing of graphics data. Lower resolution double buffer mode is used when objects are moving, and higher resolution single buffer mode is used when objects are stationary. The user gets the benefits of double buffering while objects are in motion, and the benefit of a higher quality image when objects are stationary. No image tears appear in this case because the graphics processing system redraws the exact same image when motion ceases, however the image has more bits per pixel. The visual effect is that the picture becomes clearer when motion ceases. The graphics processor quickly switches frame buffer modes during execution, and is not constrained to specifying one mode at the start of processing.

A memory organization supports a basic page size and an extended page size. A certain portion of its memory cells are dual-addressable memory cells which may be used to provide the additional memory required for the extended pages or alternatively may be used to provide additional memory within a basic page. A memory array is preferably implemented as basic pages and directly addressed to support the basic page size. The received addresses are translated to map each extended page into a portion of a basic page to support the extended pages. In one embodiment, high order row addresses are conveyed for use as high-order column addresses, and the high-order row addresses overridden, to map each extended page into a contiguous block of basic pages.