 |
Description  |
|
|
FIELD OF THE INVENTION
This invention relates to a multilayer ceramic chip capacitor.
PRIOR ART
Multilayer ceramic chip capacitors have been widely utilized as compact,
fully reliable, high capacitance electronic parts, a number of such
capacitors being contained in a single electronic equipment. In accordance
with a recently increasing demand for smaller size, higher performance
electronic equipment, multilayer ceramic chip capacitors also encounter a
more rigorous demand toward smaller size, higher capacitance, lower cost,
and higher reliability.
The multilayer ceramic chip capacitors are generally fabricated by layering
an internal electrode-forming paste and a dielectric layer-forming paste
by sheeting, printing and similar techniques followed by concurrent firing
for integration.
Generally the internal electrodes are of conductors such as Pd and Pd
alloys although expensive palladium is partially replaced by the use of
relatively inexpensive base metals such as Ni and Ni alloys. Since
internal electrodes of base metals are oxidized if fired in ambient air,
the dielectric layers and internal electrode layers must be co-fired in a
reducing atmosphere. Firing in a reducing atmosphere, however, causes the
dielectric layers to be reduced, resulting in a lowering of resistivity.
Non-reducible dielectric materials are thus proposed.
Multilayer ceramic chip capacitors using non-reducible dielectric
materials, however, have problems including a short life of insulation
resistance (IR) and low reliability.
When the dielectric material is subject to a DC electric field, there
arises another problem that its specific inductive capacity
.epsilon..sub.s lowers with time. If thinner dielectric layers are used in
order to provide chip capacitors of a smaller size and greater
capacitance, application of DC voltage across the capacitor causes the
dielectric layers to receive a stronger electric field, resulting in a
more remarkable change of specific inductive capacity .epsilon..sub.s with
time, that is, a more remarkable change of capacitance with time. Also
thinner dielectric layers are likely to dielectric breakdown.
Capacitors are also required to have good DC bias performance. The term DC
bias performance used herein is a percent change of capacitance of a chip
capacitor from the capacitance with an AC electric field applied thereto
to the capacitance with an overlapping DC electric field applied thereto.
The capacitance generally decreases as the applied DC electric field is
increased. Capacitors with poor DC bias performance have the problem that
when a DC electric field is applied across the capacitors during normal
operation, the capacitors lower their capacitance significantly to below
the standard capacitance.
The EIA standards prescribe the standard known as X7R property that the
percent change of capacitance should be within .+-.15% (reference
temperature 25.degree. C.) over the temperature range between -55.degree.
C. and 125.degree. C.
One dielectric material known to meet the X7R property is a composition of
the BaTiO.sub.3 +SrTiO.sub.3 +MnO system disclosed in Japanese Patent
Application Kokai (JP-A) No. 36170/1986. This material, however,
experiences a great change of capacitance with time under a DC electric
field, for example, a capacitance change of -10% to -30% when a DC
electric field of 50 volts is applied at 40.degree. C. for 1,000 hours,
failing to meet the X7R property.
Other non-reducible dielectric ceramic compositions include the BaTiO.sub.3
+MnO+MgO system disclosed in JP-A 71866/1982, the (Ba.sub.1-x Sr.sub.x
O).sub.a Ti.sub.1-y Zr.sub.y O.sub.2
+.alpha.((1-z)MnO+zCoO)+.beta.((1-t)A.sub.2 O.sub.5 +tL.sub.2
O.sub.3)+wSiO.sub.2 system disclosed in JP-A 250905/1986 wherein A is Nb,
Ta or V and L is Y or a rare earth element, and barium titanate having
added thereto Ba.sub..alpha. Ca.sub.1-.alpha. SiO.sub.3 in vitreous state
disclosed in JP-A 83256/1990. However, these dielectric ceramic
compositions could not meet all the requirements including a good
temperature response of capacitance, a minimized change of capacitance
with time under a DC electric field, good DC bias performance, and a long
accelerated life of insulation resistance. For example, the compositions
of JP-A 250905/1986 and 83256/1990 have a short accelerated life of
insulation resistance.
Under such circumstances, we proposed in U.S. Ser. No. 08/090,257 a
multilayer ceramic chip capacitor comprising dielectric layers which
contain barium titanate as a major component and specific amounts of
magnesium oxide, yttrium oxide, at least one of barium oxide and calcium
oxide, and silicon oxide as minor components.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a multilayer ceramic chip
capacitor which satisfies X7R property or a temperature response of
capacitance and shows a minimal change of capacitance with time under a DC
electric field, a long accelerated life of insulation resistance (IR), and
good DC bias performance. Another object of the invention is to provide
such a multilayer ceramic chip capacitor which has resistance to
dielectric breakdown in addition to the above advantages.
These and other objects are achieved by the present invention which is
defined below as (1) to (9).
(1) A multilayer ceramic chip capacitor having a capacitor chip comprising
alternately stacked dielectric layers and internal electrode layers,
wherein
said dielectric layer contains barium titanate as a major component and
magnesium oxide, yttrium oxide, at least one selected from barium oxide
and calcium oxide, and silicon oxide as minor components in such a
proportion that there are present
MgO: 0.1 to 3 mol
Y.sub.2 O.sub.3 : more than 0 to 5 mol
BaO+CaO: 2 to 12 mol
SiO.sub.2 : 2 to 12 mol
per 100 mol of BaTiO.sub.3, provided that the barium titanate, magnesium
oxide, yttrium oxide, barium oxide, calcium oxide, and silicon oxide are
calculated as BaTiO.sub.3, MgO, Y.sub.2 O.sub.3, BaO, CaO, and SiO.sub.2,
respectively,
said dielectric layer has a mean grain size of up to 0.45 .mu.m, and
in an X-ray diffraction chart of said dielectric layer, a diffraction line
of (200) plane and a diffraction line of (002) plane at least partially
overlap one another to form a wide diffraction line which has a half-value
width of up to 0.35.degree..
(2) The multilayer ceramic chip capacitor of (1) wherein said dielectric
layer has a mean grain size of at least 0.10 .mu.m and the wide
diffraction line has a half-value width of at least 0.10.degree..
(3) The multilayer ceramic chip capacitor of (1) or (2) wherein the
proportion of those crystal grains in which domain walls are observable
for presence is 35 to 85% in a section of said dielectric layer.
(4) The multilayer ceramic chip capacitor of any one of (1) to (3) wherein
said dielectric layer further contains manganese oxide as a minor
component in such a proportion that there is present up to 0.5 mol of MnO
per 100 mol of BaTiO.sub.3, provided that the manganese oxide is
calculated as MnO.
(5) A multilayer ceramic chip capacitor having a capacitor chip comprising
alternately stacked dielectric layers and internal electrode layers,
wherein
said dielectric layer contains barium titanate as a major component and
magnesium oxide, yttrium oxide, at least one selected from barium oxide
and calcium oxide, silicon oxide, manganese oxide, and at least one
selected from vanadium oxide and molybdenum oxide as minor components in
such a proportion that there are present
MgO: 0.1 to 3 mol
Y.sub.2 O.sub.3 : more than 0 to 5 mol
BaO+CaO: 2 to 12 mol
SiO.sub.2 : 2 to 12 mol
MnO: more than 0 to 0.5 mol
V.sub.2 O.sub.5 : 0 to 0.3 mol
MoO.sub.3 : 0 to 0.3 mol
V.sub.2 O.sub.5 +MoO.sub.3 : more than 0 mol
per 100 mol of BaTiO.sub.3, provided that the barium titanate, magnesium
oxide, yttrium oxide, barium oxide, calcium oxide, silicon oxide,
manganese oxide, vanadium oxide, and molybdenum oxide are calculated as
BaTiO.sub.3, MgO, Y.sub.2 O.sub.3, BaO, CaO, SiO.sub.2, MnO, V.sub.2
O.sub.5, and MoO.sub.3, respectively.
(6) The multilayer ceramic chip capacitor of (5) wherein said dielectric
layer has a mean grain size of up to 0.45 .mu.m, and in an X-ray
diffraction chart of said dielectric layer, a diffraction line of (200)
plane and a diffraction line of (002) plane at least partially overlap one
another to form a wide diffraction line which has a half-value width of up
to 0.35.degree..
(7) The multilayer ceramic chip capacitor of (6) wherein said dielectric
layer has a mean grain size of at least 0.10 .mu.m and the wide
diffraction line has a half-value width of at least 0.10.degree..
(8) The multilayer ceramic chip capacitor of (6) or (7) wherein the
proportion of those crystal grains in which domain walls are observable
for presence is 35 to 85% in a section of said dielectric layer.
(9) The multilayer ceramic chip capacitor of any one of (1) to (8) wherein
said internal electrode layer comprises a conductor in the form of nickel
or a nickel alloy.
The present invention ensures that a multilayer ceramic chip capacitor
satisfies X7R property on a temperature response of capacitance and shows
a minimal change of capacitance with time under a DC electric field, a
long accelerated life of insulation resistance (IR), and good DC bias
performance as reported in the above-referred U.S. Ser. No. 08/090,257.
In the first form of the invention, the dielectric layers have a mean grain
size of up to 0.45 .mu.m and specific characteristics in terms of X-ray
diffraction, thereby further improving the change of capacitance with time
under a DC electric field. Consequently, fully high reliability is
obtained even when dielectric layers are reduced in thickness so that the
electric field strength becomes higher. Also the reduction of the mean
grain size leads to an improvement in accelerated life of IR.
In the second form of the invention, the dielectric layers contain a
specific amount of vanadium oxide and/or molybdenum oxide, thereby further
improving the change of capacitance with time under a DC electric field.
The addition of vanadium oxide leads to an improved dielectric breakdown
voltage and the addition of molybdenum oxide leads to an improved
accelerated life of IR. Also where the dielectric layers have a mean grain
size of up to 0.45 .mu.m and specific characteristics in terms of X-ray
diffraction in the second form, the change of capacitance with time under
a DC electric field and the accelerated life of IR are further improved as
in the first form.
As mentioned above, the multilayer ceramic chip capacitor of the present
invention ensures fully high reliability even when dielectric layers are
reduced in thickness so that the electric field strength becomes higher.
It is noted that improvements in the change of capacitance with time under
a DC electric field and the accelerated life of IR are acknowledged in the
samples of Examples in the above-referred U.S. Ser. No. 08/090,257
although these measurements are made under more moderate conditions than
in Examples of the present invention to be described later. The samples of
Examples in the above-referred U.S. Ser. No. 08/090,257 wherein the
dielectric layers have a mean grain size of more than 0.45 .mu.m and the
wide diffraction line has a half-value width of more than 0.35.degree.
will fail to achieve fully satisfactory results if measurements are made
under severer conditions as in Examples of the present invention.
"Multilayer Ceramic Capacitors", Gakuken K. K., pages 33-38, describes a
report about "low temperature firing barium titanate." In the report, fine
barium titanate powder is prepared using various techniques and sintered
bodies having a grain size of 0.3 to 0.8 .mu.m are obtained by adding CuO,
Bi.sub.2 O.sub.3, PbO or the like followed by liquid phase sintering. The
report describes sintered bodies having a grain size overlapping the mean
grain size range defined in the present invention although no reference is
made to diffraction lines of (200) and (002) planes in X-ray diffraction
charts of dielectric layers. Unlike the dielectric layer composition
according to the present invention, the sintered barium titanate bodies
with a grain size of 0.3 to 0.8 .mu.m described in the report cannot be
fired in a reducing atmosphere, precluding the use of inexpensive nickel
electrodes.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view showing one exemplary structure of a
multilayer ceramic chip capacitor according to the invention.
FIGS. 2(a) and 2(b) are figure-substituting photographs or scanning
electron photomicrographs in cross section of a dielectric layer in a
multilayer ceramic chip capacitor.
FIGS. 3(a) and 3(b) are figure-substituting photographs or scanning
electron photomicrographs of BaTiO.sub.3 powder used to form the
dielectric layers of FIG. 2.
FIG. 4 is a X-ray diffraction chart of dielectric layers in multilayer
ceramic chip capacitors.
FIG. 5(a) and 5(b) are figure-substituting photographs or transmission
electron photomicrographs of a dielectric layer in a multilayer ceramic
chip capacitor.
FIG. 6 is a figure-substituting photograph or scanning electron
photomicrograph in cross section of a dielectric layer in a multilayer
ceramic chip capacitor.
FIG. 7 is a X-ray diffraction chart of a dielectric layer in a multilayer
ceramic chip capacitor.
FIG. 8 is a figure-substituting photograph or transmission electron
photomicrograph of a dielectric layer in a multilayer ceramic chip
capacitor.
BEST MODE FOR CARRYING OUT THE INVENTION
The illustrative construction of the present invention is described in
detail.
Multilayer ceramic chip capacitor
FIG. 1 shows in cross section one exemplary structure of a multilayer
ceramic chip capacitor according to the invention.
As seen from FIG. 1, the multilayer ceramic chip capacitor 1 of the
invention includes a capacitor chip 10 having a plurality of alternately
stacked dielectric layers 2 and internal electrode layers 3. The capacitor
1 further includes external electrodes 4 disposed on the side surfaces of
the capacitor chip 10 and in electrical connection to the internal
electrode layers 3. The shape of capacitor chip 10 is not critical
although it is often rectangular shaped. Also the size is not critical and
the chip may have appropriate dimensions in accordance with a particular
application, typically in the range of 1.0-5.6 mm.times.0.5-5.0
mm.times.0.5-1.9 mm. The internal electrode layers 3 are stacked such that
they at opposite ends are alternately exposed at opposite side surfaces of
the capacitor chip 10. The external electrodes 4 are applied to the
opposite side surfaces of the capacitor chip 10 to constitute a desired
capacitor circuit.
Dielectric layer 2
In the first embodiment, the dielectric layers 2 contain barium titanate as
a major component and magnesium oxide, yttrium oxide, at least one of
barium oxide and calcium oxide, and silicon oxide as minor components.
In the second embodiment, the dielectric layers 2 contain barium titanate
as a major component and magnesium oxide, yttrium oxide, at least one of
barium oxide and calcium oxide, silicon oxide, manganese oxide, and at
least one of vanadium oxide and molybdenum oxide as minor components.
Provided that barium titanate is calculated as BaTiO.sub.3, magnesium oxide
as MgO, yttrium oxide as Y.sub.2 O.sub.3, barium oxide as BaO, calcium
oxide as CaO, silicon oxide as SiO.sub.2, manganese oxide as MnO, vanadium
oxide as V.sub.2 O.sub.5, and molybdenum oxide as MoO.sub.3, the
dielectric layer contains these components in such a proportion that there
are present per 100 mol of BaTiO.sub.3, in the first form,
MgO: 0.1 to 3 mol, preferably 0.5 to 2.0 mol
Y.sub.2 O.sub.3 : more than 0 to 5 mol, preferably 0.1 to 5 mol, more
preferably more than 1 to 5 mol, most preferably 1.1 to 3.5 mol
BaO+CaO: 2 to 12 mol, preferably 2 to 6 mol
SiO.sub.2 : 2 to 12 mol, preferably 2 to 6 mol
and in the second form,
MgO: 0.1 to 3 mol, preferably 0.5 to 2.0 mol
Y.sub.2 O.sub.3 : more than 0 to 5 mol, preferably 0.1 to 5 mol, more
preferably more than 1 to 5 mol, most preferably 1.1 to 3.5 mol
BaO+CaO: 2 to 12 mol, preferably 2 to 6 mol
SiO.sub.2 : 2 to 12 mol, preferably 2 to 6 mol
MnO: more than 0 to 0.5 mol, preferably 0.01 to 0.4 mol
V.sub.2 O.sub.5 : 0 to 0.3 mol, preferably 0 to 0.25 mol
MoO.sub.3 : 0 to 0.3 mol, preferably 0 to 0.25 mol
V.sub.2 O.sub.5 +MoO.sub.3 : more than 0 mol, preferably 0.01 to 0.3 mol,
more preferably 0.05 to 0.25 mol.
The oxidation state of each oxide is not critical insofar as the contents
of metal elements constituting the respective oxides are within the
above-defined ranges.
Another compound may be contained in the dielectric layers 2 although it is
preferred that the material is substantially free of cobalt oxide because
its presence leads to an increased change of capacitance.
Described below are the reasons for the limitation of the contents of the
respective minor components.
With magnesium oxide contents below the above-defined range, it is
difficult to provide a minimal change with time of capacitance. Magnesium
oxide contents above the above-defined range drastically detract from
sinterability and thus lead to less densification, resulting in a shorter
accelerated IR life and a lower specific inductive capacity.
Yttrium oxide is effective for improving the accelerated IR life and DC
bias performance. Lesser contents of yttrium oxide provide less addition
effect, especially insufficient DC bias performance. Yttrium oxide
contents above the above-defined range result in a reduced specific
inductive capacity and detracts from sinterability, leading to less
densification.
Less contents of BaO+CaO below the above-defined range result in a greater
change of capacitance with time upon application of a DC electric field
and a shorter accelerated IR life and fail to provide a desirable
temperature response of capacitance. Larger contents of these components
result in a shorter accelerated IR life and a drastic lowering of specific
inductive capacity. Less contents of SiO.sub.2 below the above-defined
range detract from sinterability, leading to less densification whereas
contents above the range result in too low initial insulation resistance.
Manganese oxide is effective for densification of dielectric layers and
improving an accelerated IR life. With too larger contents of manganese
oxide, it is difficult to reduce a change of capacitance with time under
an applied DC electric field. Manganese oxide may be added in the first
embodiment too. Preferably manganese oxide is contained in an amount of up
to 0.5 mol, more preferably up to 0.4 mol calculated as MnO per 100 mol of
BaTiO.sub.3. To be fully effective, manganese oxide should preferably be
contained in an amount of at least 0.01 mol.
Vanadium oxide and molybdenum oxide are effective for improving a percent
change of capacitance with time under a DC electric field. Additionally,
vanadium oxide is effective for improving a dielectric breakdown voltage
and molybdenum oxide is effective for improving an accelerated IR life.
Too large contents of at least one of V.sub.2 O.sub.5 and MoO.sub.3 result
in an extreme drop of initial IR.
The dielectric layer may further contain aluminum oxide which enables
sintering at relatively low temperatures. Aluminum oxide is preferably
contained in an amount of up to 1% by weight of the dielectric layer
calculated as Al.sub.2 O.sub.3. Larger amounts of aluminum oxide would
result in a noticeable lowering of specific inductive capacity and at the
same time, a short accelerated IR life.
In the first embodiment, the dielectric layer has a mean crystal grain size
of up to 0.45 .mu.m, preferably up to 0.35 .mu.m. In the second embodiment
too, a mean grain size within this range is preferred. Such a submicron
mean grain size leads to reduced crystal anisotropy and hence, a smaller
change of capacitance with time. A submicron mean grain size also leads to
an improved accelerated life of IR. No particular lower limit is imposed
on the grain size although a smaller mean grain size must be accomplished
using a dielectric raw powder having a corresponding very small size,
which is difficult to form a paste. For this reason, usually the
dielectric layer preferably has a mean grain size of at least 0.10 .mu.m.
It is noted that the mean grain size of the dielectric layer is determined
by polishing the dielectric layer, chemically or thermally etching the
polished surface, and calculating the size from a scanning electron
photomicrograph by planimetry.
The dielectric layer consists of crystal grains which are of the tetragonal
system near room temperature. A reduction of crystal anisotropy means an
approach to the cubic system. The degree of anisotropy of crystals is
determinable by X-ray diffractometry of the dielectric layer. As crystals
reduce anisotropy, a diffraction line of (200) plane shifts toward a low
angle side and a diffraction line of (002) plane shifts toward a high
angle side so that both the diffraction lines overlap one another at least
in part. Where the mean grain size is below 0.45 .mu.m, usually the two
diffraction lines are not apparently observed as independent lines and
instead, a wide diffraction line is observed between the position of a
diffraction line of (200) plane (2.theta.=approximately 45.4.degree.) and
the position of a diffraction line of (002) plane (2.theta.=approximately
44.9.degree.). In the first embodiment, this wide diffraction line has a
half-value width of up to 0.35.degree., preferably up to 0.30.degree.. The
second embodiment also favors a half-value width in such a range. If the
half-value width is too large, the reduction of crystal anisotropy is
insufficient. No particular lower limit is imposed on the half-value width
although the half-value width is usually at least 0.15.degree. because it
is difficult to obtain a half-value width of less than 0.10.degree.. For
X-ray diffractometry, CuK.alpha..sub.1 ray is used.
Where crystals have relatively great anisotropy, the peak of a diffraction
line of (200) plane and the peak of a diffraction line of (002) plane are
sometimes observed as independent. Then there usually results a wide
diffraction line wherein the peak of a diffraction line of (002) plane
appears at the shoulder of a diffraction line of (200) plane. In this
case, the width of the wide diffraction line cut at a height equal to one
half of the highest peak is the half-value width of this wide diffraction
line.
Where the mean grain size is below 0.45 .mu.m, the proportion of those
crystal grains in which domain walls are observable as being present in a
transmission electron photomicrograph of a section of the dielectric layer
is preferably 35 to 85%, more preferably 35 to 50%. Higher proportions of
those crystal grains in which domain walls are observable would lead to
larger changes of capacitance with time.
It is preferred that elements are locally distributed in the crystal grains
of the dielectric layer. Some elements are concentrated at the center of
crystal grains while other elements are concentrated at the periphery of
crystal grains. However, it is difficult to definitely confirm such a
local distribution in an image under an electron microscope.
The dielectric layers have an appropriate Curie temperature which is
determined in accordance with the applicable standards by suitably
selecting a particular composition. Typically the Curie temperature is
higher than 85.degree. C., especially about 120.degree. to 135.degree. C.
No particular limit is imposed on the thickness of each dielectric layer.
The application of the present invention permits the dielectric layer to
be less than 4 .mu.m thick and even less than 2 .mu.m thick while
maintaining a less change of capacitance with time and full reliability.
Where the layers are formed by a printing technique, the lower limit of
thickness is usually about 0.5 .mu.m. The number of dielectric layers
stacked is generally from 2 to about 300.
Internal electrode layer 3
The conductor of which the internal electrode layers 3 are formed is not
critical although a base metal may be used since the material of the
dielectric layers 2 has anti-reducing properties. Preferred base metals
used as the conductor are nickel and nickel alloys. Preferred nickel
alloys are alloys of nickel with at least one member selected from Mn, Cr,
Co and Al, with such nickel alloys containing at least 95% by weight of
nickel being more preferred.
It is to be noted that nickel and nickel alloys may contain up to about
0.1% by weight of phosphorus and other trace components.
The thickness of the internal electrode layers may be suitably determined
in accordance with a particular application although it is typically about
0.5 to 5 .mu.m, especially about 0.5 to 2.5 .mu.m.
External electrode 4
The conductor of which the external electrodes 4 are formed is not critical
although inexpensive metals such as nickel, copper and alloys thereof may
be used in the practice of the invention.
The thickness of the external electrodes may be suitably determined in
accordance with a particular application although it is preferably about
10 to 50 .mu.m.
Preparation of multilayer ceramic chip capacitor
The multilayer ceramic chip capacitor of the present invention is
fabricated by forming a green chip by conventional printing and sheeting
methods using pastes, firing the chip, and printing or transferring
external electrodes thereto followed by baking.
Dielectric layer-forming paste
Paste for forming dielectric layers is obtained by mixing a raw dielectric
material with an organic vehicle.
For the raw dielectric material, there are used powders corresponding to
the composition of dielectric layers. The procedure for preparing the raw
dielectric material is not critical. For example, a procedure of mixing
BaTiO.sub.3 synthesized by hydrothermal synthesis or similar method with
minor component raw materials may be used. Also useful are a dry synthesis
procedure of calcining a mixture of BaCO.sub.3, TiO.sub.2 and minor
component raw materials, followed by solid phase reaction and a
hydrothermal synthesis procedure. It is also acceptable to synthesize the
raw dielectric material by calcining a mixture of a precipitate obtained
by co-precipitation, sol-gel, alkali hydrolysis and precipitate mixing
methods and minor component raw materials. The minor component raw
materials used herein may be oxides and at least one of various compounds
which convert to oxides upon firing, for example, carbonates, oxalates,
nitrates, hydroxides, and organometallic compounds.
The mean particle size of the raw dielectric material may be determined in
accordance with the desired mean grain size of dielectric layers. Since
little grain growth occurs in the composition system used in the
invention, a powder having a mean particle size of up to 0.4 .mu.m is
generally used as the raw dielectric material in order that the dielectric
layers may have a mean grain size of up to 0.45 .mu.m. It is noted in this
regard that the raw dielectric material preferably has a specific surface
area of at least 2.5 m.sup.2 /g as measured by BET.
The organic vehicle is a binder in an organic solvent. The binder used for
the organic vehicle is not critical and may be suitably selected from
conventional binders such as ethyl cellulose. Also the organic solvent
used herein is not critical and may be suitably selected from conventional
organic solvents such as terpineol, butyl carbitol, acetone and toluene in
accordance with a particular application method such as a printing or
sheeting method.
Internal electrode layer-forming paste
Paste for forming internal electrode layers is prepared by mixing
conductors such as conductive metals and alloys as mentioned above or
various compounds which convert into such conductors upon firing, for
example, oxides, organometallic compounds and resinates with organic
vehicles as mentioned above.
External electrode-forming paste
Paste for forming external electrodes may be prepared by the same method as
the internal electrode layer-forming paste.
Organic vehicle content
No particular limit is imposed on the organic vehicle content of the
respective pastes mentioned above. There may be used conventional
contents, for example, about 1 to 5% by weight of the binder and about 10
to 50% by weight of the solvent. If desired, the respective pastes may
contain other additives such as dispersants, plasticizers, dielectric
compounds and insulating compounds. The total content of these additives
is preferably up to 10% by weight.
Preparation of green chips
Where a printing method is employed, a green chip is prepared by
alternately printing the dielectric layer-forming paste and the internal
electrode layer-forming paste onto a substrate of PET or the like in
laminar form, cutting the laminar stack to a predetermined shape and
separating it from the substrate.
Where a sheeting method is employed, a green chip is prepared by forming
green sheets from the dielectric layer-forming paste, printing the
internal electrode layer-forming paste on the respective green sheets,
stacking the printed green sheets, and cutting to a predetermined shape.
Binder removal step
Binder removal prior to firing may be carried out under conventional
conditions, preferably under the following conditions where the internal
electrode layers are formed of a base metal conductor such as nickel and
nickel alloys.
Heating rate: 5.degree.-300.degree. C./hour, especially
10.degree.-100.degree. C./hour
Holding temperature: 200.degree.-400.degree. C., especially
250.degree.-300.degree. C.
Holding time: 1/2-24 hours, especially 5-20 hours
Atmosphere: air
Firing step
The green chip is then fired in an atmosphere which may be properly
determined in accordance with the type of conductor in the internal
electrode layer-forming paste. Where base metals such as nickel and nickel
alloys are used as the conductor, the firing atmosphere may have an oxygen
partial pressure of 10.sup.-8 to 10.sup.-12 atm. At an oxygen partial
pressure below the range, the conductor of the internal electrode layers
can be abnormally sintered and disconnected. At an oxygen partial pressure
above the range, the internal electrode layers are likely to be oxidized.
The holding temperature during firing is preferably 1,100.degree. to
1,400.degree. C., more preferably 1,200.degree. to 1,300.degree. C. Lower
holding temperatures below the range would provide insufficient
densification whereas higher holding temperatures beyond the range can
lead to a greater change of capacitance with time upon application of a DC
electric field.
Conditions other than the above-mentioned are preferably as follows.
Heating rate: 50.degree.-500.degree. C./hour, especially
200.degree.-300.degree. C./hour
Holding time: 1/2-8 hours, especially 1-3 hours
Cooling rate: 50.degree.-500.degree. C./hour, especially
200.degree.-300.degree. C./hour
The firing atmosphere is preferably a reducing atmosphere and the
atmospheric gas is preferably a humidified mixture of N.sub.2 and H.sub.2
gases, for example.
Annealing step
Firing of the capacitor chip in a reducing atmosphere is preferably
followed by annealing. Annealing is effective for re-oxidizing the
dielectric layers, thereby significantly extending the accelerated IR
life.
The annealing atmosphere may have an oxygen partial pressure of at least
10.sup.-6 atm., preferably 10.sup.-5 to 10.sup.-4 atm. The dielectric
layers are short of re-oxidization at a low oxygen partial pressure below
the range whereas the internal electrode layers are likely to be oxidized
above the range.
The holding temperature during annealing is preferably lower than
1,100.degree. C., more preferably 500.degree. to 1,000.degree. C. Lower
holding temperatures below the range would oxidize the dielectric layers
to a less extent leading to a shorter life. Higher holding temperatures
beyond the range can cause the internal electrode layers to be oxidized
leading to a reduced capacitance and to react with the dielectric material
leading to a shorter life. Understandably the annealing step can be
accomplished simply by heating and cooling. In this case, the holding
temperature is equal to the highest temperature on heating and the holding
time is zero.
Conditions other than the above-mentioned are preferably as follows.
Holding time: 0-20 hours, especially 6-10 hours
Cooling rate: 50.degree.-500.degree. C./hour, especially
100.degree.-300.degree. C./hour
The preferred atmosphere gas used is humidified N.sub.2 gas.
For humidifying N.sub.2 gas or a gas mixture used in the binder removal,
firing and annealing steps, a wetter may be used, for example. In this
regard, water temperature is preferably about 5.degree. to 75.degree. C.
The foregoing binder removal, firing and annealing steps may be carried out
either continuously or independently.
Where the steps are continuously carried out, it is preferred to change
only the atmosphere without cooling after binder removal, raise the
temperature to the holding temperature for firing, effect firing, then
cool, change the atmosphere when the holding temperature for annealing is
reached, and effect annealing.
Where the steps are independently carried out, in the firing step, the same
atmosphere as in binder removal is used while heating to the holding
temperature for the binder removal step, and the temperature is raised
therefrom to the holding temperature to effect firing. The firing
atmosphere is maintained while cooling to the holding temperature for the
annealing step. Then the above-mentioned annealing atmosphere is used
while cooling from the holding temperature for the annealing step. Also in
the annealing step of the independent mode, the atmosphere may be changed
after heating to the holding temperature in a N.sub.2 gas atmosphere, or a
humidified N.sub.2 gas atmosphere may be used throughout the annealing
step.
Formation of external electrode
The thus obtained capacitor chip is polished at end faces by barrel
tumbling and sand blasting, for example, before the external
electrode-forming paste is printed or transferred and baked to form
external electrodes 4. Conditions for firing of the external
electrode-forming paste include a humid mixture of N.sub.2 and H.sub.2
gases, about 600.degree. to 800.degree. C., and about 10 minutes to about
1 hour, for example.
If necessary, pads are formed on the external electrodes 4 as by plating.
The multilayer ceramic chip capacitors of the invention thus prepared are
mounted on printed circuit boards, for example, by soldering before use in
various electronic equipment.
During operation of the multilayer ceramic chip capacitors of the
invention, a DC electric field of at least 0.02 V/.mu.m, often at least
0.2 V/.mu.m, more often at least 0.5 V/.mu.m and generally up to about 5
V/.mu.m is applied across the dielectric layers while an AC component is
generally applied in an overlapping manner. The capacitors experience a
minimized change of their capacitance with the lapse of time even when
such a DC electric field is applied.
EXAMPLE
Examples of the invention are given below by way of illustration.
Example 1 (first embodiment)
The following pastes were prepared.
Dielectric layer-forming paste
A raw dielectric material was prepared by wet milling BaTiO.sub.3 prepared
by a hydrothermal synthesis method with
(MgCO.sub.3).sub.4.Mg(OH).sub.2.5H.sub.2 O, MnCO.sub.3, BaCO.sub.3,
CaCO.sub.3, SiO.sub.2, and Y.sub.2 O.sub.3 in a ball mill for 16 hours. By
changing the preparation parameters, there were prepared a plurality of
raw dielectric materials having a varying mean particle size. Another raw
dielectric material was prepared using BaTiO.sub.3 prepared by a sol-gel
method. The nominal mean particle size and BET value of BaTiO.sub.3 used
in the respective dielectric materials are shown in Table 1.
A paste was prepared by milling 100 parts of each raw dielectric material,
4.8 parts of an acrylic resin, 40 parts of methylene chloride, 20 parts of
trichloroethane, 6 parts of mineral spirit, and 4 parts of acetone in a
ball mill.
Internal electrode layer-forming paste
A paste was prepared by milling 100 parts of nickel particles having a mean
particle size of 0.8 .mu.m, 40 parts of an organic vehicle (obtained by
dissolving 8 parts by weight of ethyl cellulose resin in 92 parts of butyl
carbitol), and 10 parts of butyl carbitol in a three-roll mill.
External electrode-forming paste
A paste was prepared by milling 100 parts of copper particles having a mean
particle size of 0.5 .mu.m, 35 parts of an organic vehicle (obtained by
dissolving 8 parts by weight of ethyl cellulose resin in 92 parts of butyl
carbitol), and 7 parts of butyl carbitol.
Using the respective dielectric layer-forming pastes and the internal
electrode layer-forming paste, mult | | |
