A flash memory device that can be erased and programmed electrically, the flash memory device includes an array of transistor memory cell units each has N-doped source and drain regions formed in the device substrate. An N-doped buried channel is formed in the device substrate located between the source and drain regions. A P-doped floating gate is further formed substantially above the buried channel, and a control gate is formed on top of the floating gate. The different doping pattern in the buried channel and the floating gate establishes an increased programming bias voltage for the flash device when operating in its programming mode so that programming speed of the device is faster than conventional. The device can also be fabricated in smaller dimensions with improved reliability.
6759684 - SiC semiconductor device - Owned by National Institute of Advanced Industrial Science and Technology (Tokyo,JP) Japan Science and Technology Corporation (Kawaguchi,JP)
An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (L.sub.bc) source and drain region junction depth (X.sub.j) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.
