Apparatus and method of tracking a wordline signal using a tracking circuit having a first detector biased between a first power supply voltage and a ground voltage, and a second detector biased between a second power supply voltage and the ground voltage. The first power supply voltage is greater than the second power supply voltage. The wordline signal is driven to the first power supply voltage.

A buffer circuit is provided, which suppresses the fluctuation or deviation of the power supply voltage and the ground voltage that are caused by the logic state change of an address signal applied thereto. The buffer circuit comprises (a) a first inverter circuit having the CMOS configuration; (b) a second inverter circuit having the CMOS configuration; and (c) an equalization circuit for equalizing the first output signal of the first inverter circuit and the second output signal of the second inverter circuit. Each of the first and second inverter circuits is activated or inactivated by a control signal. When the first and second inverter circuits are activated, the equalization circuit is set in the high-impedance state, in which the first inverter circuit generates a first output signal at its output terminal and the second inverter circuit generates a second output signal at its output terminal. When the first and second inverter circuits are inactivated, the equalization circuit is set in the low-impedance state, in which the output terminals of the first and second inverter circuits is connected to each other by way of the equalization circuit, resulting in the first and second output signals of the first and second inverter circuits being in an approximately intermediate or medium logic state between the first and second logic states.

An apparatus and method of tracking accesses in a synchronously accessed memory system so as to enable dynamic sense amplifiers for sensing data at optimal times is described. In one case, the apparatus is used to enable dynamic sense amplifiers in a SRAM in which a memory cell or memory cells within the memory array are accessed by a global word line and one or more sub-word lines. The apparatus includes detection circuitry for detecting when particular GWL and SWL lines are selected and enable circuitry for enabling the appropriate sense amplifier in response to the detection circuitry. Since the enable circuitry for each sense amplifier is responsive to the accessing signals for the particular cell or cells being accessed, the sense amplifier corresponding to the cell or cells being accessed will be enabled at the proper time for reading data from the accessed cell or cells so as to avoid erroneous early reading of data and to avoid delaying reading data to ensure that it is ready.

In accordance with the present invention a mode select circuit includes a bias circuit and a voltage level encoder. The mode select circuit further includes a mode select terminal capable of being selectively coupled to one or more of a plurality of configuration elements to bias the mode select terminal to one of a plurality of predesignated voltages. The bias circuit is coupled to the mode select terminal for biasing the terminal to one of the predesignated voltages when the mode select terminal is not coupled to any of the configuration elements. The voltage level encoder is coupled to the mode select terminal for providing one of a plurality of voltage level codes on a plurality of voltage level encoder output terminals in response to the mode select terminal being biased to a corresponding one of the plurality of predesignated voltages.

A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.