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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a signal processor which processes signals read from a recording medium such as a
magnetic disk. The signal processor includes a user data processing circuit having an A/D converter and a maximum likelihood decoder, and a servo data processing circuit which has an integrating circuit.
2. Description of the Related Art
There is a demand for a faster reading/writing speed for semiconductor integrated circuit devices, which process a digital signal associated with data read from a magnetic disk. Therefore, it is necessary to improve the operation speeds of a
user data processing circuit and a servo data processing circuit which are used in such semiconductor integrated circuit devices.
A system for processing signals from a magnetic disk or other communication system decodes reception signals, using a maximum likelihood decoder, which performs maximum likelihood decoding, as one type of decoding means. In a communication
system which transfers information in the form of a finite signal series, there are a plurality of transmission signal series which have probably been transmitted in association with one reception signal series. According to the maximum likelihood
decoding, the reception side determines a transmission signal which is considered most appropriate based on some evaluation standards. A reception signal is associated with a transmission signal series in accordance with the decoding rules.
When a transmission signal which is not specified by the decoding rules is sent, a decoding error occurs. By way of example, Yi represents a reception signal series and X(Yi) represents a corresponding transmission signal series. When a
transmission signal series X(Yi) has actually been transmitted and is received as a reception signal series Yi, no decoding error occurs. Given that the probability that such a event occurs is P(X(Yi), Yi), the probability PE that a decoding error
occurs is expressed by the following equation: ##EQU1## Assuming that the probabilities of occurrence of transmission signal series are all the same, P(X(Yi)) becomes constant in any decoding rule. The minimum probability p.sub.E is therefore acquired
by selecting X(Yi) which maximizes P(Yi.vertline.X(Yi)) with respect to Yi as a transmission signal series. Maximum likelihood decoding is carried out in this manner. A maximum likelihood decoder which executes this maximum likelihood decoding includes
a plurality of metric arithmetic operation circuits. Each metric arithmetic operation circuit performs an operation on a transmission signal series X(Yi) and, based on the arithmetic operation result, selects transmission data corresponding to the
transmission signal series X(Yi) from expected values of the transmission data written in a pass memory.
FIG. 1 is a block diagram showing a conventional maximum likelihood decoder. The maximum likelihood decoder has first to fourth metric arithmetic operation circuits 1a to 1d each having two inputs to respectively receive two digital signals A1
and A2, B1 and B2, C1 and C2, or D1 and D2. The first to fourth metric arithmetic operation circuits 1a-1d perform addition or subtraction of the digital signal pairs A1 and A2 to D1 and D2, and output first to fourth operation result values
respectively. The maximum likelihood decoder further has a selector 2 and a fifth arithmetic operation circuit 1e. The selector 2 receives a first control signal CL1 indicative of the value of the most significant bit (MSB) of the second operation
result value, and a second control signal CL2 indicative of the value of the MSB of the third operation result value. The selector 2 further selects one of the second to fourth operation result values in accordance with the first and second control
signals CL1 and CL2 and outputs the selected operation result value to the fifth arithmetic operation circuit 1e. The fifth arithmetic operation circuit 1e has two inputs to respectively receive the first operation result value and one of the second to
fourth operation result values. The fifth arithmetic operation circuit 1e performs addition or subtraction of the first operation result value and the operation result value selected by the selector 2, and outputs a fifth operation result value.
However, it is difficult to improve the operation speed of a maximum likelihood decoder equipped with the above-described metric arithmetic operation circuits, for the following reason. The processing from the input of the digital signal pairs
A1 and A2 through D1 and D2, to the output of the operation result value from the fifth arithmetic operation circuit 1e, requires the arithmetic operation time and the selector operation time in two stages. After the first and second control signals CL1
and CL2 are produced based on the second and third operation result values, the selector 2 selects one of the second to fourth operation result values according to those control signals CL1 and CL2. The fifth arithmetic operation circuit 1e then
performs an operation on the first operation result value and one of the second to fourth operation result values.
If the operation speed of either the second or third arithmetic operation circuit 1b or 1c is slow, the time from the generation of the first and second control signals CL1 and CL2 to the supply thereof to the selector 2 is greater. This delays
the selector operation and the arithmetic operation of the fifth arithmetic operation circuit 1e. Consequently, the operation speed of a maximum likelihood decoder having multistage metric arithmetic operation circuits becomes slower. This reduced
operation speed affects the operation speed of the overall signal processing system which reads data from a magnetic disk and makes it difficult to improve the recording density of magnetic disks.
An operation test is conducted to check the product reliability of semiconductor integrated circuit devices, including maximum likelihood decoders such as that described above. The operation test for the maximum likelihood decoder supplies a
serial signal from a testing device to a digital filter located at the preceding stage of the maximum likelihood decoder from a testing device. The maximum likelihood decoder receives the serial signal from the digital filter and decodes it. The
testing device compares the decoded data with the serial signal to determine if the maximum likelihood decoder is operating properly.
In executing the operation test on a fast maximum likelihood decoder, the testing device should supply the serial signal at a high speed. That is, the testing device should also operate at a high speed. However, it is difficult to easily
improve the operation speed of the testing device. In the operation test, generally, the internal circuit of a semiconductor integrated circuit device (LSI) operates in accordance with a scan clock signal supplied from the testing device, not a system
clock signal. To date, however, the operation test of an LSI which operates in response to a system clock signal having a high frequency, cannot be conducted using a scan clock signal having a lower frequency than the system clock signal. In
particular, for a fast LSI equipped with digital and analog circuits, as the ratio of the analog circuits to the digital circuits increases, a sufficient operation test cannot be accomplished with the slow testing device.
A signal processor which processes a read signal read from a magnetic disk includes a user data signal processing circuit, including the aforementioned maximum likelihood decoder, and a servo signal processing circuit. The user data signal
processing circuit converts an analog signal, associated with user data included in the read signal, to a digital signal, and then performs a decoding operation on the digital signal and outputs data information to a disk controller. The disk controller
extracts user data from the received data information. The servo signal processing circuit processes a servo signal associated with servo control and included in the read signal, and outputs servo information to the disk controller. Based on this servo
information, the disk controller controls the drive head to position the head on the target track.
The servo signal processing circuit and user data signal processing circuit share an auto gain control amplifier (AGC) and a filter. The servo signal has a low frequency characteristic and the signal associated with user data has a high
frequency characteristic. In this respect, the AGC has both low and high frequency characteristics and the ability to switch between the two. The filter has switchable first and second frequencies, the first one for cutting off a frequency higher than
that of the servo signal and the second one for cutting off a frequency higher than that of the signal associated with user data. Under the servo operation, the frequency characteristic of the AGC is switched to the low frequency characteristic and the
cutoff frequency of the filter is switched to the first frequency. In a read mode, the frequency characteristic of the AGC is switched to the high frequency characteristic and the cutoff frequency of the filter is switched to the second frequency. The
switching of the frequency characteristic of the AGC and the switching of the cutoff frequency of the filter are executed in response to a control signal from the disk controller. However, it takes time to perform switching operation of the AGC and
filter, which hinders an improvement to the signal processing speed of the hard disk drive system.
The user data signal processing circuit further includes an A/D converter, which is connected to the filter and converts a read signal that is treated as an analog signal to a digital signal having a plurality of bits. It is desirable that the
A/D converter have a characteristic such that the value of the input analog signal and the value of the digital signal are positively proportional to each other. Due to a productional variation, however, some of manufactured A/D converters may have an
offset voltage so that a digital value and an analog value are not positively proportional to each other. Using such an A/D converter having an offset voltage, it is difficult to perform highly accurate processing of a read signal supplied from the
drive head. Therefore, the offset voltage is canceled either at the time of factory shipment of semiconductor integrated circuit devices, each of which include a signal processing circuit having an A/D converter, or at the time such signal processing
circuit is operated. For instance, the offset of an A/D converter may be canceled immediately after the disk drive is powered on.
The long usage of a disk drive increases the temperature of the peripheral circuits of the A/D converter, thus resulting in a variation in the input/output characteristic of the A/D converter. The ratio of the change increases as the ambient
temperature increases. This variation undesirably produces an offset voltage again, even though the offset canceling process has been performed once. Moreover, an A/D converter which is designed to output a digital signal having multi-bits (e.g., 6
bits) has a relatively large circuit area. This inevitably increases the circuit area of the associated semiconductor integrated circuit device and hinders improvements on the operation speed and conversion precision of the A/D converter.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention relates to a semiconductor integrated circuit device which operates at a high speed.
The invention also relates to a semiconductor integrated circuit device which allows a fast operation test to be performed although a test clock signal has a relatively low frequency.
In addition, the invention relates to a signal processor which processes data signals at a high speed.
The invention further relates to a signal processor capable of canceling an offset voltage of an A/D converter under any circumstances.
The invention also relates to a semiconductor integrated circuit device which prevents a circuit area from increasing and ensures a faster operation speed.
A first embodiment of the invention pertains to a digital arithmetic operation circuit including a plurality of arithmetic operation blocks for receiving a plurality of digital input signals and for performing different arithmetic operations on
the received digital input signals, in parallel, to output operation result signals, a control signal generator for receiving a plurality of digital input signals and for generating a control signal based on the digital input signals, and a selector,
connected to the plurality of arithmetic operation blocks and the control signal generator, for selecting one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal
generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.
The first embodiment of the invention also pertains to a maximum likelihood decoder including a plurality of arithmetic operation blocks for receiving a plurality of digital input signals and for performing maximum likelihood decoding operations
on the received digital input signals, in parallel according to a carry save system, to output decoded signals, a control signal generator for receiving a plurality of digital input signals and for performing an arithmetic operation on the received
digital input signals according to a carry look ahead system, to generate a control signal indicative of a most significant bit of an operation result, and a selector, connected to the plurality of arithmetic operation blocks and the control signal
generator, for selecting one of the decoded signals in response to the control signal, to output the selected decoded signal.
The first embodiment of the invention further pertains to a semiconductor integrated circuit including an analog equalizer filter for receiving an analog signal and for adjusting a level of the analog signal to output an equalized filtered analog
signal, an A/D converter, connected to the analog equalizer filter, for converting the equalized filtered analog signal to a digital signal, a digital filter, connected to the A/D converter, for receiving the digital signal and for removing an
unnecessary digital components from the digital signal to output a filtered digital signal, a maximum likelihood decoder, connected to the digital filter, for receiving the filtered digital signal and for performing a maximum likelihood decoding
operation on the received filtered digital signal to generate a serial decoded signal, a serial-parallel converter, connected to the maximum likelihood decoder, for converting the serial decoded signal to a parallel decoded signal, and a channel
characteristic generator, operatively connected to the maximum likelihood decoder in a test mode, for receiving a test signal supplied from an external testing device and for generating a test version of the filtered digital signal from the test signal,
wherein in the test mode, the maximum likelihood decoder receives the test filtered digital signal and performs maximum likelihood decoding thereon.
A second embodiment of the invention pertains to a semiconductor integrated circuit device including an input data holding circuit for temporarily holding an input data signal and for outputting the held input data signal in accordance with a
system clock signal, an internal circuit block, connected to the input data holding circuit, for receiving the input data signal and for performing a predetermined data processing operation to output an output data signal in accordance with the system
clock signal, an output data holding circuit, connected to the internal circuit block, for temporarily holding the output data signal and for outputting the held output data signal in accordance with the system clock signal, and an external interface
circuit connected to the internal circuit block, the input data holding circuit and the output data holding circuit and responsive to a scan clock signal, for generating a test clock signal having a frequency higher than that of the scan clock signal and
equal to or higher than that of the system clock signal. The input data holding circuit and the output data holding circuit are operable in accordance with the scan clock signal having a frequency lower than the system clock signal. The external
interface circuit supplies the scan clock signal and a test data signal to the input data holding circuit in such a way that the test data signal, as the input data signal, is temporarily held and is output in accordance with the scan clock signal,
supplies the test clock signal to the internal circuit block in such a way that the test data signal is processed in accordance with the test clock signal, and supplies the scan clock signal to the output data holding circuit in such a way that a test
result signal, as an output data signal, is temporarily held and is output in accordance with the scan clock signal.
A third embodiment of the invention pertains to a signal processor suitable for processing a user data signal, associated with data information read from a recording medium, and a servo data signal associated with servo information read from the
recording medium. The signal processor includes a user data signal processing circuit for processing the user data signal and a servo data signal processing circuit for processing the servo data signal. The user data signal processing circuit includes
a first amplifier for amplifying the user data signal to produce an amplified user data signal, and a first filter, connected to the first amplifier, for cutting off an unnecessary frequency component included in the amplified user data signal to produce
a filtered amplified user data signal. The servo data signal processing circuit includes a second amplifier for amplifying the servo data signal to produce an amplified servo data signal, and a second filter, connected to the second amplifier, for
cutting off an unnecessary frequency component included in the amplified servo data signal to produce a filtered amplified servo data signal.
The third embodiment of the invention also pertains to an integrating circuit for acquiring plural pieces of position data in order to obtain relative positions between tracks to which servo areas provided on a recording medium belong and a drive
head moving over the recording medium, each servo area including a plurality of position areas where the position data are respectively recorded. The integrating circuit includes a rectifier for rectifying position data signals read from the position
areas to produce rectified position data signals, a voltage-current converter, connected to the rectifier, for producing charge currents having current values proportional to voltage levels of the respective rectified position data signals, a main
capacitor, connected to the voltage-current converter, for performing charging with the charge currents, a main charge switch connected between the voltage-current converter and the main capacitor, and operable in such a way as to permit each of the
charge currents to be supplied to the main capacitor when each charge current is generated, a main discharge switch, connected to the main capacitor, for permitting charges, stored in the main capacitor, to be discharged after the main capacitor has
performed a charging operation, a plurality of detection capacitors, connected to the voltage-current converter, for performing charging with charge voltages respectively associated with the position areas, in cooperation with the main capacitor, the
charge voltages of the detection capacitors respectively indicating the plural pieces of position data, a plurality of subcharge switches respectively connected between the voltage-current converter and the detection capacitors and operable in such a way
as to permit supply of the associated charge currents to the main capacitor when the charge currents are produced, and a plurality of subdischarge switches, respectively connected to the plurality of subcharge switches, for permitting charges stored in
the detection capacitors to be discharged after execution of charging operations of the associated detection capacitors.
A fourth embodiment of the invention pertains to a circuit suitable for canceling an offset voltage of an A/D converter that converts an analog signal to a digital signal. The circuit includes a comparator for receiving the digital signal and
for comparing a digital value of the digital signal with a predetermined offset allowance value to output a comparison result, an arithmetic operation unit, connected to the comparator, for accumulating a predetermined offset change amount and outputting
an addition result based on the comparison result when the digital value differs from the predetermined offset allowance values, wherein the addition result is initially determined by adding the predetermined offset change amount and a predetermined
initial value, and an offset voltage generator, connected to the arithmetic operation unit, for generating an offset cancel voltage in order to cancel the offset voltage in accordance with the addition result and for supplying the offset cancel voltage
to the A/D converter.
The fourth embodiment of the invention also pertains to a circuit suitable for canceling an offset voltage of an A/D converter, the A/D converter samples an analog data signal including an analog sinusoidal signal in order to convert the analog
data signal to a digital signal. The circuit includes a sampling control circuit for controlling the A/D converter in such a manner that first and third sampling intervals and second and fourth sampling intervals for the analog sinusoidal signal become
180 degrees when the analog sinusoidal signal is supplied to the A/D converter, whereby digital signals having first through fourth digital values are output from the A/D converter in a sampling order, an arithmetic operation unit for receiving one of a
set of the first and third digital values and a set of the second and fourth digital values, and for computing an average value thereof to output the obtained average value as an offset voltage value for the A/D converter, and an offset voltage generator
for receiving the offset voltage value, for generating an offset cancel voltage to cancel the offset voltage, and for supplying the offset cancel voltage to the A/D converter.
A fifth embodiment of the invention pertains to a semiconductor integrated circuit device including an analog filter for removing an unnecessary frequency component included in an analog signal to produce a filtered analog signal, and an A/D
converter, connected to the analog filter, for performing over-sampling of the filtered analog signal according to a first frequency signal to convert the filtered analog signal to a digital signal.
The device of the fifth embodiment may include a first digital filter, connected to the A/D converter, for removing an unnecessary frequency component included in the digital signal in accordance with the first frequency signal to produce a first
filtered digital signal, and a digital phase locked loop, connected to the A/D converter and the first digital filter, for generating the first frequency signal and for supplying the first frequency signal to the A/D converter and the first digital
filter.
The device of the fifth embodiment may further include a first register, connected to the first digital filter and the digital phase locked loop, for intermittently sampling the first filtered digital signal in accordance with a second frequency
signal to produce a first thinned digital signal. The digital phase locked loop may include a voltage controlled oscillator for generating the first frequency signal in response to a voltage signal, and a frequency divider for frequency-dividing the
first frequency signal to produce the second frequency signal.
The device of the fifth embodiment may also include a second digital filter, connected to the first sampling register and the digital phase locked loop, for removing an unnecessary frequency component included in the first thinned digital signal
in accordance with the second frequency signal to produce a second filtered digital signal.
The device of the fifth embodiment may further include a second register, connected to the second digital filter and the digital phase locked loop, for intermittently sampling the second filtered digital signal in accordance with a third
frequency signal to produce a second thinned digital signal. The digital phase locked loop may further include a second frequency divider, connected to the first frequency divider, for frequency-dividing the second frequency signal to produce the third
frequency signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating the principles of the invention by way of example.
BRIEF DESCRIPTION OF
THE DRAWINGS
The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings.
FIG. 1 is a block diagram showing a conventional maximum likelihood decoder;
FIG. 2 is a block diagram showing a digital arithmetic operation circuit according to the first embodiment of the present invention;
FIG. 3 is a block diagram depicting a data reading circuit in a magnetic disk drive;
FIG. 4 is a block diagram illustrating a first metric arithmetic operation unit in a maximum likelihood decoder according to the first embodiment of this invention;
FIG. 5 is a block diagram showing a second metric arithmetic operation unit in the maximum likelihood decoder according to the first embodiment of this invention;
FIG. 6 is a block diagram showing a third metric arithmetic operation unit in the maximum likelihood decoder according to the first embodiment of this invention;
FIG. 7 is a block diagram depicting a control signal generator in the maximum likelihood decoder according to the first embodiment of this invention;
FIG. 8 is a block diagram illustrating a data reading circuit including a test circuit for the maximum likelihood decoder;
FIG. 9 is a circuit diagram showing a transfer path characteristic generator as a test circuit;
FIG. 10 is a block diagram showing a general semiconductor IC device which covers first to sixth examples of the second embodiment of the invention;
FIG. 11 is a block diagram showing a semiconductor IC device according to the first example;
FIG. 12 is a block diagram showing a semiconductor IC device according to the second example;
FIG. 13 is a block diagram showing a semiconductor IC device according to the third example;
FIG. 14 is a block diagram showing a semiconductor IC device according to the fourth example;
FIG. 15 is a block diagram showing a semiconductor IC device according to the fifth example;
FIG. 16 is a block diagram showing a semiconductor IC device according to the sixth example;
FIG. 17 is a block diagram showing a semiconductor IC device according to the seventh example;
FIG. 18 is a block diagram showing the basic structure of a magnetic disk apparatus;
FIG. 19 is a block diagram illustrating a signal processor according to the third embodiment of this invention;
FIG. 20 is a block diagram showing a servo signal processor according to the third embodiment of this invention;
FIG. 21 is a block diagram showing a track hold circuit in the servo signal processor;
FIG. 22 is a waveform chart used for explaining the operation of a zero-cross detector in the servo signal processor;
FIG. 23 is a time chart used for explaining the operation of an integration circuit in the servo signal processor;
FIG. 24 is a time chart used for explaining the operation of the integration circuit when an abnormality occurs;
FIG. 25 is a diagram illustrating the format of a servo area defined on a magnetic disk;
FIG. 26 is a schematic block circuit diagram of a magnetic disk drive according to the fourth embodiment of this invention;
FIG. 27 is a diagram showing the recording format of each sector of a magnetic disk;
FIG. 28 is a block diagram depicting a data information processor incorporated in the magnetic disk drive according to the first example of the fourth embodiment;
FIG. 29 is a graph illustrating the relationship between the input voltage and output voltage of an A/D converter;
FIG. 30 is a block diagram depicting a data information processor incorporated in the magnetic disk drive according to the second example of the fourth embodiment;
FIG. 31 is a diagram showing a sampling signal and a read signal which is associated with a preamble pattern to be sampled in accordance with this sampling signal;
FIG. 32 is a schematic block diagram illustrating a recorded data reproducing apparatus which reads data written on a magnetic disk according to the fifth embodiment of this invention;
FIG. 33 is a block diagram of a phase difference detector included in a read channel IC which is provided in the recorded data reproducing apparatus;
FIG. 34A is a diagram showing over-sampling of a read analog data signal according to a first sampling clock signal;
FIG. 34B is a diagram showing intermittent sampling of a first digital data signal associated with the read analog data signal;
FIG. 34C is a diagram showing intermittent sampling of a second digital data signal associated with the read analog data signal;
FIG. 35 is a diagram for explaining the estimation of sampling points of a first digital data signal;
FIG. 36 is a diagram for explaining the computation of the inclination of a wave form of the first digital data signal;
FIG. 37 is a diagram showing sampling when there is no phase difference between a sampling point of interest and the optimal sampling point;
FIG. 38 is a diagram showing sampling when the phase of a sampling point of interest lags from that of the optimal sampling point;
FIG. 39 is a diagram showing sampling when the phase of a sampling point of interest leads that of the optimal sampling point;
FIG. 40A is a diagram illustrating the generation of a second sampling signal in a normal state;
FIG. 40B is a diagram illustrating the generation of a pulse-inserted second sampling signal in a normal state; and
FIG. 40C is a diagram illustrating the generation of a pulse-deleted second sampling signal in a normal state.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
FIG. 2 illustrates a multi-input digital arithmetic operation circuit according to the present invention. The digital arithmetic operation circuit has first through third arithmetic operation blocks 141a through 141c, first and second control
signal generators 142a and 142b, and a selector 143. The first through third arithmetic operation blocks 141a-141c receive a digital input signal Din and perform different arithmetic operations from one another, to supply operation results to the
selector 143. In response to the digital input signal Din, the first and second control signal generators 142a and 142b respectively produce first and second control signals CTL1 and CTL2 and supply the signals to the selector 143. The selector 143
selects one of the operation results from the first through third arithmetic operation blocks 141a-141c in accordance with the first and second control signals CTL1 and CTL2, and outputs the selected operation result. In this manner, an operation on the
digital input signal Din and the generation of the first and second control signals CTL1 and CTL2 are executed in parallel. This parallel operation permits the selector 143 to selectively supply one of the operation results from the first to third
arithmetic operation blocks 141a-141c immediately upon reception of the operation results.
A description of this invention adapted to a maximum likelihood decoder will be now described. FIG. 3 is a block diagram depicting a data reading circuit included in a magnetic disk drive. The magnetic disk drive has a read head 111, an
amplifier 112 and a read channel IC 113 as a data reading circuit. The read channel IC 113 includes a gain control amplifier 114, an analog equalizer filter 115, an A/D converter 116, a digital filter 117, a maximum likelihood decoder 118, a PLL
synthesizer 119 and a serial-parallel converter 140.
The read head 111 reads an analog data signal, written on a magnetic disk 110, and supplies it to the amplifier 112. The amplifier 112 amplifies the analog data signal and supplies the amplified analog data signal to the gain control amplifier
114. The gain control amplifier 114 controls the gain of the amplified analog data signal in response to a gain compensation signal gc supplied from an external control apparatus (not shown), and supplies the gain-compensated analog data signal having a
predetermined amplitude to the analog equalizer filter 115. This filter 115 adjusts the signal level in such a way that the gain-compensated analog data signal has a predetermined frequency characteristic, and sends the filtered analog data signal to
the A/D converter 116. The A/D converter 116 converts the filtered analog data signal to a digital signal, which is in turn supplied to the digital filter 117. The digital filter 117 removes the unnecessary digital component from the digital signal and
sends the filtered digital signal to the maximum likelihood decoder 118. The maximum likelihood decoder 118 performs a decoding operation according to the maximum likelihood decoding algorithm to produce a decoded serial read data signal, and supplies
this signal to the serial-parallel converter 140. The serial-parallel converter 140 converts the serial signal to a parallel signal and supplies the latter signal to an external processor (not shown) which is connected to the read channel IC 113. The
digital filter 117 also supplies the filtered digital signal to the PLL synthesizer 119, which in turn produces a sampling frequency signal for the A/D converter 116 in accordance with the filtered digital signal and sends the sampling frequency signal
to the A/D converter 116.
As shown in FIGS. 4 to 7, the maximum likelihood decoder 118 includes first to third metric arithmetic operation units 150 through 152 and a control signal generator 153. The first metric arithmetic operation unit 150, shown in FIG. 4, has first
through third subtracting circuits 119a through 119c, first through fourth registers 120a through 120d, four first arithmetic operation blocks 121a through 121d, one second arithmetic operation block 122a, one third arithmetic operation block 123a, and
first and second selectors 127a and 127b. These components of the first metric arithmetic operation unit 150 operate in response to clock signals. The second metric arithmetic operation unit 151, shown in FIG. 5, has fourth and fifth subtracting
circuits 119d and 119e, fifth and sixth registers 120e and 120f, two first arithmetic operation blocks 121e and 121f, two second arithmetic operation blocks 122b and 122c, one fourth arithmetic operation block 124a, one fifth arithmetic operation block
125, and third and fourth selectors 127c and 127d. These components of the second metric arithmetic operation unit 151 also operate in response to clock signals. The third metric arithmetic operation unit 152, shown in FIG. 6, has a sixth subtracting
circuit 119f, seventh through ninth registers 120g through 120i, two third arithmetic operation blocks 123b and 123c, one fourth arithmetic operation block 124b, fifth through seventh selectors 127e to 127g, and first through third adders 126a through
126c. These components of the third metric arithmetic operation unit 152 also operate in response to clock signals.
Each of the first arithmetic operation blocks 121a-121f has four input terminals for respectively receiving four signals (denoted by A, B, C and D), and an output terminal for supplying a signal (denoted by F) representing the operation result,
and executes an operation of F=A-B-C+D. Each of the second arithmetic operation blocks 122a-122c has three input terminals for respectively receiving three signals (denoted by A, B and C), and an output terminal for supplying a signal (denoted by F)
representing the operation result, and executes an operation of F=A-B-C. Each of the third arithmetic operation blocks 123a-123c has three input terminals for respectively receiving three signals (denoted by A, B and C), and an output terminal for
supplying a signal (denoted by F) representing the operation result, and executes an operation of F=A-B+C. Each of the fourth arithmetic operation blocks 124a and 124b has four input terminals for respectively receiving four signals (denoted by A, B, C
and D), and an output terminal for supplying a signal (denoted by F) representing the operation result, and executes an operation of F=A-B+C+D. The fifth arithmetic operation block 125 has four input terminals for respectively receiving four signals
(denoted by A, B, C and D), and an output terminal for supplying a signal (denoted by F) representing the operation result, and executes an operation of F=A-B-C-D.
Each of the first through fifth arithmetic operation blocks 121a-121f through 125 is a multi-input arithmetic operation block according to a known carry save system. Each arithmetic operation block has an array of adders arranged in a plurality
of stages, so that a carry generated in each adder at the first stage is supplied to an adder of a higher bit at the second stage, not a higher-bit adder at the first stage. The arithmetic operation block, which performs a multi-input addition using a
plurality of two-input adders, sequentially supplies carries generated in the adders of individual bits to the higher-bit adders. Therefore, the arithmetic operation time from the beginning to the end of the arithmetic operation for all the bits
coincides with the sum of the operation delay times of the individual adders. In an arithmetic operation block which utilizes the carry save system, the arithmetic operation time becomes shorter than the sum of the operation delay times of the
individual adders, and can thus be shortened.
In the first metric arithmetic operation unit 150 illustrated in FIG. 4, the first register 120a temporarily stores a series of reception signals Yi supplied as the filtered digital signal from the digital filter 117, and supplies the signal
series as a first register output signal to the second subtracting circuit 119b and the first arithmetic operation blocks 121a-121c. The first register 120a further supplies the fourth register output signal XX to the first subtracting circuit 119d of
the second metric arithmetic operation unit 151. The first subtracting circuit 119a subtracts a reference signal Ref having a specific reference voltage from the reception signal series Yi, and supplies the subtraction result to the second register
120b. The second register 120b temporarily stores the subtraction result supplied from the subtracting circuit 119a, and supplies this subtraction result as a second register output signal to the third subtracting circuit 119c and the first through
third arithmetic operation blocks 122a, 123a, 121d. The second register 120b also supplies the second register output signal XX1 to the fourth subtracting circ | | |
