A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.

A method of forming a carbon doped oxide layer on a substrate is described. That method comprises introducing into a chemical vapor deposition apparatus a precursor gas that is selected from those having the formula (CH.sub.3).sub.x Si(OCH3).sub.4-x. Simultaneously, a background gas, oxygen and nitrogen are introduced into the chemical vapor deposition apparatus. That apparatus is then operated under conditions that cause a carbon doped oxide layer to form on the substrate.

A method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide layer is developed based upon the physics of deposition and sputtering and based upon the minimum geometry of features in the semiconductor device. First the geometric parameters of the metal features are determined. Then, based upon the most aggressive aspect ratio between metal lines, the deposition rate to sputter rate ratio is calculated. The film thickness for optimum global planarity is determined based on the calculated ratio. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.

A method of manufacturing an insulating layer 30 (IMD layer) that has a uniform etch rate and forms improved via/contact opening profiles. The method forms a coating film 11 of silicon oxide over the chamber walls 22 of a CVD reactor. Next, the wafer 12 is loaded into the CVD reactor 20. A first insulating layer 30 composed of oxide preferably formed by a sub-atmospheric undoped silicon glass (SAUSG) using TEOS is formed over the semiconductor structure 12. Via/Contact Openings 32 are then etched in the insulating layer 30. The coating film 11 over the interior surfaces (e.g., reactor walls) 22 improves the etch rate uniformity of the first insulating layer 30. The first insulating layer 30 is preferably a inter metal dielectric (IMD) layer.

A method for improving interlayer dielectric to metal layer adhesion including an in-situ plasma treatment process. A metal layer which is formed on a substrate is treated with plasma prior to the deposition of the interlayer dielectric. The interlayer dielectric is deposited above the metal layer and contacts are formed through the interlayer dielectric which electrically connect the underlying metal layer to a subsequently formed metal layer. The plasma treatment step creates open molecular bonds on the surface of the metal layer which cause the interface between the metal layer and the interlayer dielectric to become more adhesive. Thus, decreasing the likelihood of delamination that degrades the electrical reliability of the device.