An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

An address selection circuit in a synchronous memory device receives a clock signal and an address signal, passes the received address signal asynchronously from an address input circuit to an address decoder to generate an address selection signal, then uses the same received address signal to generate further address selection signals in synchronization with the clock signal. This scheme enables the address selection signals to be generated more quickly than if all address signal paths were synchronized with the clock signal. In a burst access, even the first address selection signal can be generated relatively quickly.

A column select line control circuit for a synchronous semiconductor memory device increases the time margin for writing input data to memory cells in prefetch mode by delaying the disablement of the column select lines during a write operation, thereby extending the time for writing data to the cells. The control circuit includes a column select line control circuit that generates enable and disable signals in response to an internal clock signal, and a column decoder that enables and disables a column select line in response to the enable and disable signals. In pipeline mode, the column select line control circuit generates the disable signal by delaying the internal clock signal and generates the enable signal by delaying and inverting the internal clock signal. In prefetch mode, the column select line control signal adds an additional delay to both the enable and disable signals, but only during write operations.

Power usage of an integrated circuit including an embedded memory array is reduced significantly by preventing a clock signal from clocking unaccessed memory blocks in the embedded memory array while allowing the clock signal to clock the currently accessed memory block. In an exemplary embodiment, the clock signal is gated with individual memory block enable signals such that the clock signal clocks only the currently enabled or accessed memory block. Only one memory block or a limited number of memory blocks out of an array of memory blocks on a data bus is clocked or operated at any one time. In another embodiment, a delay circuit delays the removal of the clock signal to the accessed memory block until a period of time after the enable signal to the memory block is removed. Thus, the accessed or enabled memory block is allowed to clock internally substantially only during a time corresponding to when that memory block is enabled or accessed.

In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.