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Method for monitoring metal corrosion on integrated circuit wafers
   
Document Number
US Patent 5874309
Issued Date
February 23, 1999
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Abstract
A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.
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Number of Claims:
10
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Published
February 23, 1999
Application Number
08/730,383
Filed
October 16, 1996
US Classification
436/6   436/1 436/5
Int'l Classification
G01N   17/00   (20060101)   G01N   33/00   (20060101)  
USPTO Field of Search
436/6   436/1   436/5  
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