Multi-processor data processing system with multiple second level caches mapable to all of addressable memory

Claims

We claim:

1. A method for maintaining cache coherency in a shared memory multiprocessor data processing system, wherein the system includes a first processor coupled to a first cache and a second processor coupled to a second cache, and the first processor issues a write function code to the first cache, the write function code specifying data and a memory address at which to store the data, the method comprising the steps of:

invalidating the memory address in the second cache if the memory address was not last modified at the first cache;

writing the data in the first cache;

designating the memory address in the first cache as last-modified in the first cache; and

inhibiting said invalidating the memory address in the second cache for subsequent write function codes issued by the first processor and referencing the memory address in the first cache while the memory address is designated as last-modified in the first cache.

2. A method for maintaining cache coherency in a shared memory multiprocessor data processing system, wherein the system includes a first processor coupled to a first first-level cache and a second processor coupled to a second first-level cache, the first first-level cache being coupled to a first second-level cache, the second first-level cache being coupled to a second second-level cache, the first second-level cache being coupled to the second second-level cache, and the first processor issues a write function code to the first first-level cache, the write function code specifying data and a memory address at which to store the data comprising the steps of:

invalidating the memory address in the second second-level cache if the memory address was not last modified in the first second-level cache;

writing the data in the first second-level cache,

designating the memory address as last modified in the first second-level cache; and

inhibiting invalidating the memory address in the second second-level cache for subsequent write function codes issued by the first processor and referencing the memory address in the first second-level cache while the memory address is designated as last-modified in the first second-level cache.

3. A cache architecture for a multiprocessor data processing system, wherein the system includes a plurality of instruction processors for executing instructions and for issuing read and write function codes and address codes for reading and writing data stored in a shared memory, the cache architecture comprising:

a plurality of first-level cache means, each mappable to all addresses of the shared memory and coupled to a different respective one of the instruction processors for receiving the address codes;

first second-level cache means mappable to all addresses of the shared memory, directly coupled to the shared memory and coupled to first predetermined ones of said plurality of first-level cache means for receiving the address codes from said first predetermined ones of said plurality of first-level cache means;

second second-level cache means mappable to all addresses of the shared memory, directly coupled to the shared memory, coupled to second predetermined ones of said plurality of first-level cache means for receiving the address codes from said second predetermined ones of said plurality of first-level cache means, and directly coupled to said first second-level cache means, said second second-level cache means for receiving the address codes from said first second-level cache means, and said first second-level cache means for receiving the address codes from said second second-level cache means;

first coherency logic means coupled to said first second-level cache means and coupled to said first predetermined ones of the plurality of first-level cache means for providing a first invalidation signal to said second second-level cache means when an address in said first second-level cache means is written;

second coherency logic means coupled to said second second-level cache means and coupled to said second predetermined ones of the plurality of first-level cache means for providing a second invalidation signal to said first second-level cache means when an address in said second second-level cache means is written;

first filter means coupled to said first coherency logic means for preventing said first coherency logic means from providing said first invalidation signal if an address in said first second-level cache means is written and said address was last-modified in said first second-level cache means; and

second filter means coupled to said second coherency logic means for preventing said second coherency logic means from providing said second invalidation signal if an address in said second second-level cache means is written and said address was last-modified in said second second-level cache means.

4. The cache architecture of claim 3, further comprising:

first second-level cache tag means coupled to said first second-level cache means having a first plurality of address entry means, each of said first plurality of address entry means for indicating a respective one or more addresses of the shared memory that are cached in said first second-level cache means;

a first plurality of last-modified indicator means, each associated with a different respective one of said first plurality of address entry means for indicating whether said respective one or more addresses of the shared memory that are cached in said first second-level cache means were last written in said first second-level cache means;

second second-level cache tag means coupled to said second second-level cache means having a second plurality of address entry means, each of said second plurality of address entry means for indicating one or more addresses of the shared memory that are cached in said second second-level cache means; and

a second plurality of last-modified indicator means, each associated with a different respective one of said second plurality of address entry means for indicating whether said respective one or more addresses of the shared memory that are cached in said second second-level cache means were last written in said second second-level cache means.

5. The cache architecture of claim 3, further comprising:

first first-level cache tag means associated with said first predetermined ones of the plurality of said first-level cache means;

second first-level cache tag means associated with said second predetermined ones of the plurality of said first-level cache means;

first duplicate tag means coupled to said first first-level cache tag means and coupled to said first coherency logic means; and

second duplicate tag means coupled to said second first-level cache tag means and coupled to said second coherency logic means.

6. A cache system for a multiprocessor data processing system, wherein the data processing system includes a plurality of instruction processors for providing address signals to a shared memory to thereby read data signals from, or write data signals to, selectable addresses within the shared memory, the cache system, comprising:

a plurality of first-level caches, each mappable to all of the addresses of the shared memory and coupled to a respective one of the instruction processors for receiving the address signals from said respective one of the instruction processors;

a first second-level cache mappable to all of the addresses of the shared memory, uniquely directly coupled to the shared memory and coupled to a first set of predetermined ones of said plurality of first-level caches for receiving the address signals from said first set of predetermined ones of said plurality of first-level caches;

a first coherency logic circuit coupled to said first second-level cache and coupled to said first set of predetermined ones of said plurality of first-level caches, capable of providing a first invalidation signal to said second second-level cache and to said second set of predetermined ones of said plurality of said first-level caches when an address in said first second-level cache is written;

a second second-level cache mappable to all of the addresses of the shared memory, uniquely directly coupled to the shared memory, coupled to a second set of predetermined ones of said plurality of first-level caches for receiving the address signals from said second set of predetermined ones of said plurality of first-level caches, and uniquely directly coupled to said first second-level cache, said second second-level cache being capable of receiving the address signals from said first second-level cache, and said first second-level cache being capable of receiving the address signals from said second second-level cache;

a second coherency logic circuit coupled to said first coherency logic circuit, coupled to said second second-level cache, and coupled to said second set of predetermined ones of said plurality of first-level caches capable of providing a second invalidation signal to said first second-level cache and to said first set of predetermined ones of said plurality of said first-level caches when an address in said second second-level cache is written;

a first filter circuit coupled to said first coherency logic circuit to prevent said first coherency logic circuit from providing said first invalidation signal if an address cached in said first second-level cache is written and said address was last-modified in said first second-level cache; and

a second filter circuit coupled to said second coherency logic circuit to prevent said second coherency logic circuit from providing said second invalidation signal if an address cached in said second second-level cache is written and said address was last-modified in said second second-level cache.

7. A cache architecture for a data processing system, wherein the system includes a plurality of units and a shared memory, the plurality of units for making requests for data stored in the shared memory, the cache architecture, comprising:

a first cache directly coupled to the shared memory and mappable to all addresses of the shared memory, said first cache coupled to first predetermined ones of the plurality of units to receive first requests to access selected ones of the shared memory addresses;

a second cache directly coupled to the shared memory and mappable to all addresses of the shared memory, said second cache coupled to second predetermined ones of the plurality of units to receive second requests to access selected ones of the shared memory addresses, said second cache coupled to said first cache to allow said second cache to provide predetermined ones of said second requests to said first cache, and to allow said first cache to provide predetermined ones of said first requests to said second cache; and

a first filter circuit coupled to said first cache to prevent any of said predetermined ones of said first requests which is a request to access a shared memory address for which the contents were last modified within said first cache from causing said first cache to provide an invalidation request to said second cache.

8. The cache architecture of claim 7, and further including a second filter circuit coupled to said second cache to prevent any of said predetermined ones of said second requests requesting access to a shared memory address for which the contents were last modified within said second cache from causing said second cache to provide an invalidation request to said first cache.

9. The cache architecture of claim 8, and further including a first coherency control circuit coupled to said first cache to store a first set of last-modified indicators, each of said first set of last-modified indicators associated with respective ones of the shared memory addresses to indicate whether the contents of said respective ones of the shared memory addresses were last-modified within said first cache.

10. The cache architecture of claim 9, wherein said first coherency control circuit includes a first control circuit to receive each of said predetermined ones of said second requests, and in response to said each of said predetermined ones of said second requests, to reset an associated one of said first set of last-modified indicators which is associated with the shared memory address for which access was requested.

11. The cache architecture of claim 10, and further including a second coherency control circuit coupled to said second cache to store a second set of last-modified indicators, each of said second set of last-modified indicators associated with respective ones of the shared memory addresses to indicate whether the contents of said respective ones of the shared memory addresses were last-modified within said second cache.

12. The cache architecture of claim 11, wherein said second coherency control circuit includes a second control circuit to receive each of said predetermined ones of said first requests, and in response to said each of said predetermined ones of said first requests, to reset an associated one of said second set of last-modified indicators which is associated with the shared memory address for which access was requested.

13. A cache architecture for use in a data processing system including a shared memory, and a plurality of instruction processors, the plurality of instruction processors for providing memory addresses to address the shared memory, the cache architecture, comprising:

a first cache memory coupled to the shared memory and being mappable to all memory addresses within the shared memory, said first cache memory to receive first ones of the memory addresses provided by first ones of the plurality of instruction processors, said first cache memory to store data signals associated with said first ones of the memory addresses;

a second cache memory coupled to the shared memory and being mappable to all memory addresses within the shared memory, said second cache memory to receive second ones of the memory addresses provided by second ones of the plurality of instruction processors, said second cache memory to store data signals associated with said second ones of the memory addresses, said second cache memory being coupled to said first cache memory, and whereby said first cache memory provides ones of said first memory addresses as first invalidation requests to said second cache memory, said first invalidation requests to invalidate ones of the data signals stored within said second cache memory when data signals associated with said ones of said first memory addresses are modified within said first cache memory; and

a first filter circuit coupled to said first cache memory to prevent any of said ones of said first memory addresses that are associated with data signals for which the most recently updated copy is stored in said first cache memory from being provided as first invalidation requests to said second cache memory.

14. The cache architecture of claim 13, wherein said second cache memory provides ones of said second memory addresses as second invalidation requests to said first cache memory, said second invalidation requests to invalidate ones of the data signals stored within said first cache memory when said data signals associated with said ones of said second memory addresses are modified within said second cache memory; and

a second filter circuit coupled to said second cache memory to prevent any of said ones of said second memory addresses that are associated with data signals for which the most recently updated copy is stored in said second cache memory from being provided as second invalidation requests to said first cache memory.

15. The cache architecture of claim 14, and further including a first storage device coupled to said first cache memory to store a first set of last-modified signals, each of said first set of last-modified signals associated with first respective ones of the memory addresses to indicate whether the contents of said first respective ones of the memory addresses were last-modified within said first cache memory.

16. The cache architecture of claim 15, and further including a second storage device coupled to said second cache memory to store a second set of last-modified signals, each of said second set of last-modified signals associated with second respective ones of the memory addresses to indicate whether the contents of said second respective ones of the memory addresses were last-modified within said second cache memory.

17. The cache architecture of claim 16, and further including:

a first tag storage device coupled to said first cache memory to store first invalidation indicators, each of said first invalidation indicators associated with respective ones of the memory addresses stored in said first cache memory to indicate whether said respective ones of the memory addresses stored in said first cache memory have been designated as invalidated in said first cache memory; and

a second tag storage device coupled to said second cache memory to store second invalidation indicators, each of said second invalidation indicators associated with respective ones of the memory addresses stored within said second cache memory to indicate whether said respective ones of the memory addresses stored within said second cache memory have been designated as invalidated in said second cache memory.

18. The cache architecture of claim 13, wherein said first cache memory and second cache memory are second-level cache memories, and further including:

a first first-level cache memory coupled to said first cache memory and coupled to said first ones of the plurality of instruction processors to receive said first ones of the memory addresses, said first first-level cache memory to provide said first ones of the memory addresses to said first cache memory if the contents of said first ones of the memory addresses are not stored in said first first-level cache memory; and

a second first-level cache memory coupled to said second cache memory and coupled to said second ones of the plurality of instruction processors to receive said second ones of the memory addresses, said second first-level cache memory to provide said second ones of the memory addresses to said second cache memory if the contents of said second ones of the memory addresses are not stored in said second first-level cache memory.

19. A cache architecture for a data processing system, wherein the system includes a memory and a plurality of units for making requests to read from, or write to, the memory, the cache architecture, comprising:

first cache means for storing first selected ones of the memory addresses, said first cache means for receiving first requests from first predetermined ones of the plurality of units to read from, or write to, said first selected ones of the memory addresses;

second cache means for storing second selected ones of the memory addresses, said second cache means for receiving second requests from second predetermined ones of the plurality of units to read from, or write to, said second selected ones of the memory addresses, said second cache means for generating a first invalidation request to send to said first cache means when the contents of any one of said second selected ones of the memory addresses are being modified in said second cache means; and

filter means for preventing said invalidation request from being sent to said first cache means if said second cache means is storing the latest copy of the contents of said any one of said second selected ones of the memory addresses which is being modified.

20. The cache architecture of claim 19, wherein said first cache means includes circuits for generating a second invalidation request to send to said second cache means when the contents of any one of said first selected ones of the memory addresses are being modified in said first cache means, and further comprising second filter means for preventing said second invalidation request from being sent to said second cache means if said first cache means is storing the latest copy of said any one of said first selected ones of the memory addresses which is being modified.

21. The cache architecture of claim 20, and further comprising

first storage means for storing a first set of last-modified indicators, each of said last-modified indicators in said first set for indicating whether the contents of respective ones of said first selected ones of the memory addresses are last modified in said first cache means; and

second storage means for storing a second set of last-modified indicators, each of said last-modified indicators in said second set for indicating whether the contents of respective ones of said second selected ones of the memory addresses are last modified in said second cache means.