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Description  |
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FIELD OF THE INVENTION
The present invention relates to a power network simulation and analysis
tool for testing the reliability of the physical designs of integrated
circuit semiconductor chips.
BACKGROUND OF THE INVENTION
A highly specialized field, commonly referred to as "electronic design
automation" (EDA), has evolved to handle the demanding and complicated
task of designing semiconductor chips. In EDA, computers are extensively
used to automate the design process. Computers are ideally suited to
performing tasks associated with the design process because computers can
be programmed to reduce or decompose large, complicated circuits into a
multitude of much simpler functions. Thereupon, the computers can be
programmed to iteratively solve these much simpler functions. Indeed, it
has now come to the point where the design process has become so
overwhelming that the next generation of integrated circuit (IC) chips
cannot be designed without the help of computer-aided design (CAD)
systems.
And after the circuit for a new semiconductor chip has been designed and
physically laid out, there still remains extensive testing which must be
performed to verify that this new design and layout works properly. A
multitude of different combinations of test vectors are applied as inputs
to the design in order to check that the outputs are correct. In the past,
many prior art testing and reliability tools assumed a constant power
supply voltage source. This approach was deficient because although the
design might be functioning perfectly from a logic standpoint, it might,
nevertheless, still not meet specifications due to hidden voltage drop and
electromigration problems in interconnect wires. In real life, each of the
transistors of a semiconductor circuit consumes a small amount of power
(during the logic switching period.). Individually, the voltage drop in
the power network attributable to a single transistor is negligible.
However, due to rapid advances in semiconductor technology, today's chips
can contain upwards of ten million or more transistors. The cumulative
effect of all these voltage drops may lead to serious performance
degradation or even critical failures. For example, a transistor might be
specified to be a logic "0" from 0.0 to 0.7 volts and to be a logic "1"
from 3.3 to 2.1 volts. However, due to the voltage drops in the power
network, a transistor output might not switch to those specified ranges
and thus results in a logic error. And even if a voltage-tolerant CMOS
process is used whereby the transistor has more noise margin, its
switching speed is detrimentally impacted. Higher power supply voltages
makes transistors switch faster, whereas lower voltages makes them switch
slower. Consequently, if the voltage in a power network of a circuit drops
below a critical level, the speed of that circuit might be reduced to an
unacceptable rate.
Another problem which might arise relates to electromigration. It has been
established that high current density can cause the metal in the lines
distributing the power through the semiconductor chip to migrate along the
path of the current flow. Eventually, over a period of time (e.g., several
years), this electromigration can result in an open circuit so that power
is cut off from parts of the IC, thereby causing the IC to fail. The
electromigration may even result in a short circuit which also causes the
IC to fail.
Thus, it would be prudent to test for any potential power distribution
problems as part of the overall testing and simulation process. However,
testing a circuit with millions of transistors is an extremely complex and
time-consuming process. It requires expert knowledge and highly skilled
EDA specialists. Furthermore, it requires the dedication of a powerful and
expensive mainframe computer with gigabytes of memory. Indeed, advances in
semiconductor technology has led to submicron designs having even greater
numbers of transistors being crammed into ever greater densities at higher
levels of complexities which threaten the capability of today's most
powerful computers to simulate.
Thus, there exists a need in the prior art for some reliability analysis
tool to test and simulate gigantic power network of multi-million
transistor submicron IC designs. The present invention provides a unique,
efficient solution by implementing a hierarchical scheme. Basically, the
present invention extracts an accurate; yet reduced RC model of the power
network and current characteristics for each circuit block in the design
layout file and then simulates the entire power network of the design with
those derived models to determine the current flow and voltage drops in
each interconnect wire in the entire circuit at each instance of time,
that would otherwise be impossible to simulate due to the prohibitively
large memory and CPU time requirement when tried with a conventional flat
simulation method. Based on this transistor level simulation, circuit
designers can pinpoint where voltage drop and electromigration may pose
problems. The designers may then take corrective action before chips are
fabricated and sold.
SUMMARY OF THE INVENTION
The present invention pertains to a reliability analysis tool to test and
simulate the power network of submicron IC designs. A hierarchical
approach incorporating four stages is applied: block level verification,
modeling, full chip simulation, and revisiting the blocks. In the block
level verification stage, rather than analyzing the entire chip at once,
the new chip design is divided into a number of blocks at the top level.
The layout of each block matches that of the schematic. The power
connection locations of each block are identified in the chip layout.
These blocks are then analyzed for voltage drop and electromigration with
the assumption that the full voltage levels are being supplied at each
power connection point. Any problems detected during the analysis are
connected and the blocks are reanalyzed as necessary. Next, in the
modeling stage, the power network in each of the blocks is modeled as
equivalent RC network. Current characteristics at each power connection
point are also modeled as a piece wise linear function. These RC networks
are then further reduced into much simpler circuits, which can be analyzed
more easily, efficiently and quickly. The actual voltage drops and current
waveforms through the top-level interconnect wires are then determined in
the full chip RC network simulation stage based on the functionally
equivalent, but reduced RC networks and the recorded current models. Once
the actual voltage drops and current flows through the interconnect wires
have been determined, the last stage is to revisit the blocks with this
new information. Instead of assuming that the full supply voltage is being
supplied to the blocks, the actual calculated voltage drops are
substituted thereto as inputs to the various blocks. The blocks are then
re-analyzed with the updated voltage and current values to determine
whether there may exist any potential voltage, current, thermal, or
electromigration problems with any nodes or wires of the new design.
BRIEF DESCRIPTION OF THE DRAWINGS
The operation of this invention can be best visualized by reference to the
drawings.
FIG. 1 shows a flowchart describing the basic stages of the present
invention.
FIG. 2 shows a semiconductor chip which may be tested and simulated by the
present invention.
FIG. 3 is a flowchart describing in detail, the steps for performing the
block level verification.
FIG. 4 shows an exemplary block having three probe points with power lines
supplying power to the block.
FIG. 5 shows an exemplary current profile flowing through a dynamic power
connection as determined by the test vectors.
FIG. 6 shows a flowchart describing in detail, the steps for modeling the
blocks.
FIG. 7 shows a simple example of how an RC circuit can be reduced.
FIG. 8 is a flowchart describing in detail, the steps associated with the
full chip simulation stage.
FIG. 9 is a flowchart describing in detail the steps for performing the top
level simulation.
FIG. 10 is a flowchart describing in detail the steps for revisiting the
blocks.
FIG. 11 shows an exemplary computer system (e.g., personal computer,
workstation, mainframe, etc.), upon which the present invention may be
practiced.
DETAILED DESCRIPTION
A reliability analysis tool for testing and simulating the power network of
submicron IC designs is described. In the following description, for
purposes of explanation, numerous specific details are set forth in order
to provide a thorough understanding of the present invention. It will be
obvious, however, to one skilled in the art that the present invention may
be practiced without these specific details. In other instances,
well-known structures and devices are shown in block diagram form in order
to avoid obscuring the present invention.
Referring now to FIG. 1, a flowchart describing the basic stages of the
present invention is shown. Rather than simulating and analyzing all of
the chip's transistors and parasitic resistors and capacitors originating
from the interconnect wires at the same time, the present invention
performs the simulation and analysis in four basic stages 101-104. In the
first stage 101, the semiconductor chip is broken into several top level
blocks, with each block having four million or less transistors. Since the
values of the voltage drops to the power connection points have not been
calculated, it is assumed at this point that there are no voltage drops. A
block level verification is then performed on each of these blocks. Next,
stage 102 models the power RC networks of these blocks with simplified,
equivalent circuits. The simplified circuits are electrically the same as
actual circuits of the blocks that they represent, except that the total
number of components (resistors and capacitors) have been reduced. This
reduction makes it easier to analyze the RC networks of the blocks.
Thereupon, a full chip RC network simulation can be performed in stage
103. Based on this simulation, the voltage drops corresponding to each of
the blocks can now be more easily determined. In the last stage 104, the
blocks are then revisited (e.g., simulated and analyzed) with the
calculated voltage drops and current in flows.
FIG. 2 shows a ten million transistor semiconductor chip 200 as which may
be tested and simulated by the present invention. The circuits inside chip
200 are broken into sixteen separate blocks 201-216. The functions of each
of the four stages are now described in detail with reference to
semiconductor chip 200.
In particular, FIG. 3 is a flowchart describing in detail, the steps for
performing the block level verification. In the first step 301, all of the
blocks 201-216 which are to be modeled are identified. Note that not each
and every block has to be modeled in this fashion. Next, the blocks
201-216 are arranged in step 302 into subdirectories of the circuit
directory. All the blocks and the top level should be in parallel
directories. For each block, steps 303-310 are performed. In step 303, the
layout versus schematic (LVS) checking is performed to ensure that the
layout of each block matches with that of the schematic. The test vectors
for driving the blocks from the top level are then obtained, step 304. The
probe points corresponding to each of the power connection points are
generated in step 305. A probe point corresponds to the physical location
(x, y) at which power is supplied to a block. A block may have one or more
probe points. An example of three probe points 401-403 for power lines
404-406 supplying power to block 201 is shown in FIG. 4.
The next step 306 involves performing an RC extraction to determine the
equivalent RC networks of the interconnect wires. For example, a metal
line may be represented with its equivalent resistance, which is a
function of its length, width, and intrinsic properties. There are many
different tools which are commercially available for RC extraction. In the
currently preferred embodiment, the RC extraction is performed by a tool
Arcadia sold by Synopsys, Inc. of Mountain View, Calif. This particular
tool generates an .espf file for RC networks to VDD and GND. Based on this
RC network, the voltages at the nodes and branch currents can be
calculated using well-known electrical principles. Once the voltages and
currents are determined, an approximate simulation of voltage drop and
electromigration analysis can be created at step 307. Based on this
simulation, potential problem areas are isolated. For example, the voltage
drop at a particular node may be too much or the current density through
one path may be too high. The user may choose in step 308 to resolve
potential voltage drop and electromigration issues by tweaking the design
or layout.
Next, the currents through the power connections or "pads" (e.g., probe
points 401-403) are captured with a "power" configuration command, step
309. Finally, step 310 generates a file (e.g., piece-wise linear--.pwl),
to store all the pad current waveforms for the block as a function of
time. At each instant in time, the currents through a pad are recorded and
a running average is calculated. After some duration of time, a sample
current waveform can be constructed. In the currently preferred
embodiment, these steps are accomplished through the use of an "em.sub.--
make.sub.-- pad.sub.-- ipwl" command to generate the .pwl file. During
block level simulation, the em.sub.-- make.sub.-- pad.sub.-- ipwl function
records a piece-wise linear current waveform for each power connection
point in the block. FIG. 5 shows an exemplary current profile flowing
through a dynamic power connection as determined by the test vectors. It
can be seen that the current fluctuates as a function of the switching
states of the transistors coupled to that particular power connection. In
step 311, the program stores all the peak voltage drops for each pad and
the average current flowing through each branch in the power network. In
the currently preferred embodiment, this step is accomplished through an
"em.sub.-- vector.sub.-- compaction" command, which compares all the
voltage drops calculated for that node to find the largest voltage drop.
For example, one set of test vectors might result in a voltage drop of
only 0.2 volts, whereas another set of test vectors might result in a
higher voltage drop of 0.7 volts. Similarly, the em.sub.-- vector.sub.--
compaction command averages all the current values over some period of
time. This information is stored in separate files (e.g., VDD.ave,
VDD.vec, GND.ave, and GND.vec). Step 312 determines whether all designated
blocks have been verified. If so, the block verification stage 101 is
completed. Otherwise, steps 303-311 are repeated for subsequent designated
blocks. It should be noted that each block can be analyzed whenever the
design of the block is finished.
FIG. 6 shows a flowchart describing in detail, the steps for modeling the
blocks. The goal of this stage 102 is to reduce the extracted RC networks
(stored as an .espf file) for the blocks to equivalent connectivity and
impedance models. In step 601, an .espf file is created from performing an
RC extraction. Next, the power connection points are specified, step 602.
The reduction is accomplished in part by first performing serial and/or
parallel reductions in step 603. The principles behind the reductions are
well known in the art. For example, FIG. 7 shows an equivalent circuit for
a simple case of an resistor/capacitor (RC) circuit reduction. By
iteratively reducing the resistors, inductors, and capacitors (RLCs), a
complex circuit can be reduced into simpler circuits that is electrically
equivalent to the original circuit. In the currently preferred embodiment,
step 603 is accomplished by running an "em.sub.-- list.sub.-- espf.sub.--
file reduction" command to generate an .spi file containing the equivalent
circuit having serial/parallel reductions. Further reductions are possible
in step 604 by applying commercially available reduction tools. One such
tool is the AWE product, manufactured and sold by Synopsis Inc. of
Mountain View, Calif. The "make.sub.-- awe" program can reduce a typical
circuit by a factor of ten. The resulting reduced, equivalent circuit is
stored in an .awl file. The power connection points were preserved during
step 310 (see FIG. 3). In the currently preferred embodiment, they are
specified as probe.sub.13 points by the em.sub.-- add.sub.-- pad comment.
Step 605 ensures that steps 601-604 are repeated for each of the blocks.
FIG. 8 is a flowchart describing in detail, the steps associated with the
full chip simulation netlist preparation stage. The first step 801 of the
full chip simulation stage 103 involves assigning probe.sub.-- points for
power connection points to the blocks. In the currently preferred
embodiment, a utility known as "top.sub.-- rail" has been developed to
generate the power connection points of all the blocks for the top level
extraction according to an input file. The input file (e.g., block.sub.--
instance file) contains one line description of each block instance. An
exemplary format might be: instance.sub.-- name block.sub.-- name x y
orientation vdd.sub.-- probe file gnd.sub.-- probe.sub.-- file. An example
of such an input file might look like: x1 ram1 5709.60 2469.40
0ram1/probe.vdd ram1/probe.vss. The composite power connection points
(probe.sub.-- points) of all the specified blocks are stored in an output
file. Next, step 802 performs the actual RC extraction for the top level
composite mode. The modeled blocks are represented as black boxes with
inputs, functions performed on the inputs, and outputs. The VDD and GND
lines terminate at the boundaries of the blocks which are modeled as black
boxes (with probe.sub.-- points assigned). In step 803, the top level
power netlist is prepared. As part of step 803, the reduced power network
is inserted to the top level power netlist for each block. This can be
achieved by using the same "top.sub.-- rail" utility which inserts a call
from the top level .espf file to the awe file for each block instance. The
port orders are matched by name. Next, step 804 prepares the blocks for
simulation. In the currently preferred embodiment, this is accomplished by
attaching em.sub.-- ipwl commands to the probe.sub.-- points locations. In
other words, the current waveforms (see FIG. 5) are applied to the power
connection points of the block instances. The "em.sub.-- ipwlfile filename
instance.sub.-- name" config command is specified to match the .pwl file
of a block to multiple instantiations. If necessary, top level vectors
will be applied. Finally, step 805 performs the top level simulation.
FIG. 9 is a flowchart describing in detail the steps for performing the top
level simulation. First, the whole chip netlist files (.espf ), including
calls to reduced .awe block files, is accessed in step 901. Next, step 902
drives the transistors contained in a top level netlist which also
includes the vectors for driving those transistors. There is no need to
include the blocks for step 902. In step 903, the em.sub.-- ipwl config
commands are applied to the appropriate probe.sub.-- points for each
block. The simulation vectors are then assigned in step 904 to drive the
transistors at the top level. At this point, step 905, the voltage drop
and current density analysis can be performed for the top level. Step 906
resolves all top level issues that have been identified. Finally, step 907
records the peak voltage drop and the average current in flow for each
power connection points for all of the blocks. It should be noted that
steps 902 and 904 are optional.
FIG. 10 is a flowchart describing in detail the steps for revisiting the
blocks. Once the voltage drops for the supplies to the blocks have been
determined (step 907), the power supplies to the blocks are adjusted based
on this new information and the block is resimulated. This is accomplished
by first applying the recorded voltage drops to the power supply
connection points for the block and then simulating the RC network for
voltage drops, steps 1001 and 1002. Next, the recorded current to the
power supply connection points for the block are applied, and the RC
network is simulated for current density, steps 1003 and 1004. A
determination is then made in step 1005 as to whether there are any
voltage drop violations that will be caused by the voltage drop at the
block connections. Similarly, the current density at each wire is
resimulated with the current flowing into the pads into consideration
(calculated in step 907). This may include new voltage drop highlight
and/or violation files as well as new current density highlight and/or
violation files, which are placed in the directory of that particular
block. If there is a violation, the designer can fix the violation by
changing either the netlist or layout geometries to modify the design,
step 1006. This may include new voltage drop highlight and/or violation
files as well as new current density highlight and/or violation files,
which are placed in the directory of that particular block. Optionally,
the user can choose to expand a block to a transistor level in step 1007.
If a block is expanded, the top level simulation is performed (see process
of FIG. 8), step 1008. The user may desire to leave the block modeled at
the top level. In either case, the number of transistors needs to be
consistent with the capacity associated with the workstation running this
tool. This process of steps 1001-1008 can be iteratively repeated for each
of the blocks, step 1009.
Referring to FIG. 11, an exemplary computer system 1112 (e.g., personal
computer, workstation, mainframe, etc.) upon which the present invention
may be practiced is shown. The reliability analysis tool to test and
simulate the power network of semiconductor chips is operable within
computer system 1112. When configured with the simulation and testing
procedures of the present invention, system 1112 becomes a computer aided
design (CAD) tool 1112, for reliability analysis. The four stages of the
present invention described in Figures are implemented within system 1112.
In general, computer systems 1112 used by the preferred embodiment of the
present invention comprise a bus 1100 for communicating information, one
or more central processors 1101 coupled with the bus for processing
information and instructions, a computer readable volatile memory 1102
(e.g., random access memory) coupled with the bus 1100 for storing
information and instructions for the central processor 1101. A computer
readable read only memory (ROM) 1103 is also coupled with the bus 1100 for
storing static information and instructions for the processor 1101. A
random access memory (RAM) 1102 is used to store temporary data and
instructions. A data storage device 1104 such as a magnetic or optical
disk and disk drive coupled with the bus 1100 is used for storing
information and instructions. A display device 1105 coupled to the bus
1100 is used for displaying information to the computer user. And an
alphanumeric input device 1106 including alphanumeric and function keys is
coupled to the bus 1100 for communicating information and command
selections to the central processor 1101. A cursor control device 1107 is
coupled to the bus for communicating user input information and command
selections to the central processor 101, and a signal input/output port
1108 is coupled to the bus 1100 for communicating with a network. The
display device 1105 of FIG. 11 utilized with the computer system 1112 of
the present invention may be a liquid crystal device, cathode ray tube, or
other display device suitable for creating graphic images and alphanumeric
characters recognizable to the user. The cursor control device 1107 allows
the computer user to dynamically signal the two dimensional movement of a
visible symbol (pointer) on a display screen of the display device 1105.
The foregoing descriptions of specific embodiments of the present invention
have been presented for purposes of illustration and description. They are
not intended to be exhaustive or to limit the invention to the precise
forms disclosed, and obviously many modifications and variations are
possible in light of the above teaching. The embodiments were chosen and
described in order to best explain the principles of the invention and its
practical application, to thereby enable others skilled in the art to best
utilize the invention and various embodiments with various modifications
as are suited to the particular use contemplated. It is intended that the
scope of the invention be defined by the claims appended hereto and their
equivalents.
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