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Method for fabricating a carrier for testing unpackaged semiconductor dice    
United States Patent5878485   
Link to this pagehttp://www.wikipatents.com/5878485.html
Inventor(s)Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID); Hembree; David R. (Boise, ID)
AbstractA method for fabricating a carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illustrative embodiment the carrier is formed with a laminated ceramic base. The ceramic base includes internal conductive lines that are wire bonded to the interconnect and metal plated external contacts that are connected to external test circuitry. In an alternate embodiment the carrier is formed with an injection molded plastic base and includes 3-D circuitry formed by a metallization and photolithographic process. In either case, the carrier is adapted for testing different die configurations by interchanging different interconnects.
   














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Patent Text Patent PDF Print Page Summary File History
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Inventor     Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID); Hembree; David R. (Boise, ID)
Owner/Assignee     Micron Technologoy, Inc. (Boise, ID)
Patent assignment
All assignments
Publication Date     March 9, 1999
Application Number     08/615,119
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     March 13, 1996
US Classification     29/825 29/846 29/848 29/856 257/E21.512 257/E21.525 257/E23.004 257/E23.069 257/E23.07 324/760 324/765
Int'l Classification     H01R 043/00
Examiner     Vo; Peter
Assistant Examiner     Chang; Rick Kiltae
Attorney/Law Firm     Gratton; Stephen A.
Address
Parent Case     CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of application Ser. No. 08/398,309 filed Mar. 1, 1995, now U.S. Pat. No. 5, 519,332 which is a continuation-in-part of application Ser. No. 08/345,064 filed Nov. 14, 1994 now U.S. Pat. No. 5,541,525, which is a continuation-in-part of application Ser. No. 08/124,899 filed Sep. 21, 1993 now U.S. Pat No. 5,495,179, which is a continuation-in-part of application Ser. No. 08/046,675, filed Apr. 14, 1993 now U.S. Pat. No. 5,367,253, which is a continuation-in-part of application Ser. No. 07/973,931 filed on Nov. 10, 1992 now U.S. Pat No. 5,302,891, which is a continuation of application Ser. No. 07/709,858, filed Jun. 4, 1991, abandoned. This application is related to applications Ser. No. 07/788,065 filed Nov. 5, 1991 now U.S. Pat No. 5,440,240; Ser. No. 07/953,750 filed Sep. 29, 1992 now abandoned; Ser. No. 08/073,005 filed Jun. 7, 1993 now U.S. Pat. No. 5,408,190; Ser. No. 08/073,003 filed Jun. 7, 1993 now abandoned; Ser. No. 08/120,628 filed Sep. 13, 1993 now abandoned; Ser. No. 07/896,297 filed Jun. 10, 1992 now U.S. Pat. No. 5,424,652; Ser. No. 08/192,391 filed Feb. 3, 1994 now U.S. Pat. No. 5,483,174; and, Ser. No. 08/137,675 filed Oct. 14, 1993 now abandoned.
Priority Data    
USPTO Field of Search     29/825 29/846 29/848 29/851 29/852 29/856 324/765 324/755 324/760
Patent Tags     fabricating carrier testing unpackaged semiconductor dice
   
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What is claimed is:

1. A method for fabricating a carrier for testing a semiconductor die, comprising:

providing an interconnect comprising a plurality of first contacts configured to electrically contact a plurality of second contacts on the die;

molding a plastic base for retaining the die for testing, the base comprising a first surface, a second surface, and a plurality of vias extending from the first surface to the second surface;

forming a plurality of first conductors on the first surface configured for electrical communication with the first contacts, and a plurality of second conductors on the second surface configured for electrical communication with external contacts on the base;

forming an electrically conductive material within the vias to electrically connect the first conductors to the second conductors; and

mounting the interconnect to the base with the first contacts in electrical communication with the first conductors and the external contacts.

2. The method of claim 1 wherein molding the base includes forming a plurality of ribs proximate to the second surface configured to support the external contacts for electrically contacting an electrical socket.

3. The method of claim 1 wherein molding the base includes forming a plurality of flanges at least partially enclosing the first surface and configured to protect a force mechanism of the carrier.

4. The method of claim 1 wherein molding the base includes forming an opening in the base for mounting a force mechanism to the base.

5. The method of claim 1 wherein forming the electrically conductive material in the vias comprises depositing a metal using a plating process.

6. The method as claimed in claim 1 further comprising during the molding step, forming a third surface on the base configured to mount a bar code for tracking the die during a test procedure.

7. A method for fabricating a carrier for testing a semiconductor die, comprising: