 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock synchronous type semiconductor
memory device which operates in synchronization with an externally applied
clock signal. More specifically, the present invention relates to a
structure of an input buffer receiving an external signal in the clock
synchronous type semiconductor memory device.
2. Description of the Background Art
Various memory LSIs (Large Scale Integrated Circuits) allowing high speed
access have been proposed to eliminate difference in speed of operation
between a microprocessor and a memory. These memory LSIs are characterized
in that effective data transfer rate is increased by inputting/outputting
data in synchronization with an external clock signal. One of such
synchronous memories operating in synchronization with an external clock
signal is a synchronous DRAM (hereinafter referred to as an SDRAM). The
SDRAM includes a memory cell generally constituted by a dynamic type
memory cell of one capacitor/one transistor.
FIG. 13 shows an example of an arrangement of external pin terminals in a
conventional SDRAM. Referring to FIG. 13, external pin terminals are
arranged on both sides along longer side direction of a rectangular
package (TSOP: Thin Small Outline Package). On opposing ends in the longer
side direction of the package, there are arranged pin terminals P1 and P23
receiving a power supply voltage Vdd, and pin terminals P2 and P24
receiving the ground voltage Vss. Adjacent to power supply pin terminal P1
and ground pin terminal P2, pin terminals P3, P4 . . . P7, and P8 for data
input/output are arranged. Between these data input/output pin terminals
P3, P4, P7 and P8, pin terminals P5, P6, and P9, P10 respectively for
supplying ground voltage VssQ and power supply voltage VddQ utilized by a
buffer circuit for data input/output are arranged.
Near the central portion of the package, pin terminals P11 to P17 receiving
external control signals are arranged. A write enable signal ZWE is
applied to pin terminal P11. A column address strobe signal ZCAS is
applied to pin terminal P13. A row address strobe signal ZRAS is applied
to pin terminal P15. A chip select signal ZCS is applied to pin terminal
P17. A reference potential Vref which serves as a reference for
determining high level and low level of an external signal in an input
buffer, which will be described later, is applied to pin terminal P12. The
reference potential Vref may be used in other form in internal circuitry.
An external clock signal CLK defining an operation timing of the SDRAM is
applied to pin terminal P14. A clock enable signal CKE defining whether
the external clock signal CLK is valid or invalid is applied to pin
terminal P16. External signal is not applied to pin terminal P18, which in
turn is kept at a no connection (NC) state.
External address signals Ad are applied to pin terminals P19, P20, P21 and
P22 at the lower portion on both sides of the package.
Different from a standard DRAM, in the SDRAM, an internal operation to be
executed is defined by the states of external control signals ZWE, ZCAS,
ZRAS and ZCS at the rise of clock signal CLK. The manner of operation will
be described in the following with reference to FIG. 14.
Referring to (a) of FIG. 14, at a rising edge of clock signal CLK, by
setting chip select signal ZCS and row address strobe signal ZRAS to the L
level and setting column address strobe signal ZCAS and write enable
signal ZWE to the H level, an active command is applied and internal
operation of the SDRAM is activated. More specifically, in accordance with
the active command, an address signal X is taken in the SDRAM, and memory
cell selecting operation in accordance with the address signal X is
started.
As shown at (b) of FIG. 14, at a rising edge of clock signal CLK, by
setting chip select signal ZCS and column address strobe signal ZCAS to
the L level and by setting row address strobe signal ZRAS and write enable
signal ZWE to the H level, a read command is applied, and a data reading
mode is designated. When the read command is applied, an address signal Y
is taken, and in SDRAM, column selection operation on the memory cells in
accordance with the address signal Y is performed, so that data Q of the
memory cell at the selected row and column is output. Generally, after the
lapse of a clock cycle period referred to as "ZCAS latency" after the
application of the read command, valid data Q is output. In (b) of FIG.
14, a state in which ZCAS latency is 1 is shown.
Referring to (c) of FIG. 14, at the rising edge of clock signal CLK, by
setting chip select signal ZCS, column address strobe signal ZCAS and
write enable signal ZWE to the L level and by setting row address strobe
signal ZRAS to the H level, a write command is applied. When the write
command is applied, data writing operation of the SDRAM is designated, and
data D in the clock cycle in which the write command is applied is taken
in the SDRAM and then written to the internal selected memory cell
designated by the address signals X and Y.
As shown at (d) of FIG. 14, at the rising edge of clock signal CLK, by
setting chip select signal ZCS, row address strobe signal ZRAS and write
enable signal ZWE to the L level and by setting column address strobe
signal ZCAS to the H level, a precharge command is applied. When the
precharge command is applied, the inner portions of the SDRAM are returned
to the precharge state, and memory cells which have been selected are all
brought to non-selected state. Internal circuits of the SDRAM are all
returned to the precharged state (standby state).
By taking in the apparatus the external signals, that is, external control
signal, address signal and write data in synchronization with the rising
edge of the clock signal CLK, internal operation can be started at high
speed without the necessity to take into consideration a timing margin
caused by a skew of the external signals, whereby high speed access is
allowed. Further, since data input/output is performed in synchronization
with the clock signal CLK, data can be written/read at high speed. Here,
generally in an SDRAM, when a read command or a write command is applied,
a number of data, which number is referred to as burst length, can be
continuously read or written in accordance with the address signal (Y
address) applied at the time of application of the command.
FIG. 15 is a block diagram schematically showing an internal structure of
the SDRAM. Referring to FIG. 15, the SDRAM includes a clock buffer 1 for
buffering an external clock signal extCLK; a CKE buffer circuit 2 for
taking and latching external clock enable signal extCKE in synchronization
with an output signal from clock buffer 1 for generating an internal clock
enable signal intCKE; and an internal clock generating circuit 4 which is
activated when internal clock enable signal intCKE is activated, for
generating an internal clock signal intCLK in accordance with an output
signal from clock buffer 1. When the internal clock enable signal intCKE
is inactive, that is, when it indicates that the external (internal) clock
signal is invalid, internal clock generating circuit 4 fixes the internal
clock signal intCLK at the L level.
The SDRAM further includes an external signal input buffer circuit 6 for
taking in and latching external signals ZCS, ZRAS, ZCAS and ZWE in
synchronization with the rise of internal clock signal intCLK for
generating an internal control signal; a command decoder 8 for generating
a signal designating an operation mode designated in accordance with the
internal control signal from external signal input buffer 6; and an
internal control signal generating circuit 10 for generating a necessary
internal control signal in accordance with an internal operation mode
designating signal from command decoder 8. Internal control signal
generating circuit 10 also operates in synchronization with internal clock
signal intCLK and activate/inactivate various internal control signals in
accordance with the internal clock signal intCLK.
The SDRAM further includes a memory cell array 12 including a plurality of
memory cells MC arranged in a matrix; an address buffer circuit 14 for
taking external address signal bits Ad0 to Adn in synchronization with
internal clock signal intCLK for generating an internal address signal; a
row selecting circuit 16 which is activated in response to an internal
control signal from internal control signal generating circuit 10 for
decoding an internal row address signal X from address buffer circuit 14
for selecting a corresponding row of memory cells in memory cell array 12;
a column selecting circuit 18 which is activated in response to an
internal control signal from internal control signal generating circuit 10
for selecting a column of memory cells in memory cell array 12 in
accordance with an internal column address signal Y from address buffer
circuit 14; a data input/output buffer circuit 20 for inputting/outputting
data to and from the inside of the memory device under the control of
internal control signal generating circuit 10; and a read/write circuit 22
for communicating data between the selected memory cell of memory cell
array 12 and data input/output buffer 20 under the control of internal
control signal generating circuit 10.
In memory cell array 12, a word line WL is arranged corresponding to each
row of memory cells, and a bit line pair BLP is arranged corresponding to
each column of memory cells MC.
Row selection related circuit 16 includes an X decoder decoding the row
address signal X, a word line driver for driving a selected word line WL
to the selected state in accordance with an output signal from the X
decoder, a sense amplifier for sensing, amplifying and latching data of
memory cell MC connected to the selected word line WL, and a circuit for
controlling activation/inactivation of the sense amplifier.
Column selection related circuit 18 includes an IO gate provided
corresponding to each bit line pair BLP, and an Y decoder decoding the
column address signal Y for selecting an IO gate.
Read/write circuit 22 includes a plurality of registers for each of data
writing and data reading and performs writing/reading of data in
synchronization with internal clock signal intCLK in response to a
write/read designating signal applied from internal control signal
generating circuit 10.
As described above, internal operation timings are all determined by the
internal clock signal intCLK. When the internal clock signal intCLK is
fixed at the L level by clock enable signal intCKE, external signal
(external write data, address signal bit and external control signal) is
not taken in, and internal control signal generating circuit 10 is kept at
the state of the previous clock cycle. There is no change in states of
internal signals, and hence signal lines are not charged/discharged, so
that current consumption can be reduced.
FIGS. 16A and 16B are charts illustrating the function of the external
clock enable signal extCKE. Referring to FIG. 16A, in clock cycle 0, when
external clock enable signal extCKE is at the H level, internal clock
signal intCLK is generated in synchronization with external clock signal
extCLK in the next clock cycle 1. The state of internal clock signal
intCLK in clock cycle 0 is determined by the state of signal extCKE in the
previous clock cycle.
In clock cycle 1, when the external clock enable signal extCKE is set to
the L level at the rising edge of external clock signal extCLK, then
internal clock intCLK is fixed at the L level in the next clock cycle 2.
More specifically, in clock cycle 2, rising of internal clock signal
intCLK is inhibited. Therefore, in clock cycle 2, SDRAM is kept at the
same state as in clock cycle 1.
FIG. 16B is an illustration representing how external clock enable signal
extCKE is utilized upon data writing/reading. In FIG. 16B, external
control signals ZCS, ZRAS, ZCAS and ZWE are collectively shown as a
command.
When external clock enable signal extCKE is set to the H level and a write
command is applied in clock cycle 1, data D0 is taken in at the rising
edge of external clock signal extCLK. When external clock enable signal
extCKE is set to the L level generation of an internal clock signal in
clock cycle 3 is stopped. In this state, even when in clock cycle 2, data
D1 is taken in in clock cycle 2 and then external clock signal extCLK
rises in clock cycle 3, next data D2 is not taken, since internal clock
signal is not generated. Therefore, a CPU (Central Processing unit) which
is an external control device applies the same data D2 in the next clock
cycle 4. Consequently, in clock cycle 4, an internal clock signal is
generated due to returning of the signal extCKE to H level and data D2 is
taken in, and in clock cycle 5, data D3 is taken in. In FIG. 16B, burst
length is set to 4 as an example. Here, the burst length means the number
of data which can be continuously written or read when a write command or
a read command is applied. Therefore, at the time of data writing, by
keeping external clock enable signal extCKE at the L level for a period of
1 clock cycle, the valid state of data D2 can be made longer, and the
write timing of data D3 can be delayed by 1 clock cycle. Even when write
data D3 is not prepared by CPU, the data write timing can be delayed until
the generation of data D3.
By utilizing external clock enable signal extCKE, when write data are
applied continuously at the rising edge of external clock signal extCLK
and data D3 is to be written in clock cycle 4 while data D3 is not yet
prepared, it becomes possible to delay the writing until data D3 is
prepared. Therefore, data can be written in accordance with the operation
timing of external CPU.
When a read command is applied in clock cycle 6 and external clock enable
signal extCKE is fixed at H level, valid data Q0 is output in clock cycle
10 after the lapse of ZCAS latency, and data Q1, Q2 and Q3 are read in
clock cycles 11, 12 and 13, respectively. Here, ZCAS latency is, for
example, 3. When external clock enable signal extCKE is set to the L level
in clock cycle 7, generation of internal clock signal is stopped in clock
cycle 8, data reading operation is stopped for one clock cycle, ZCAS
latency is made longer by 1 cycle equivalently, and hence valid data Q0 is
output after the lapse of 4 clock cycles, that is, in clock cycle 11.
When external clock enable signal extCKE is set to L level in clock cycle
11 again, generation of internal clock signal is stopped in clock cycle
12, and hence data Q1 which has internally been read in clock cycle 11 and
defined in clock cycle 12 is also kept valid in clock cycle 13. Since
external clock enable signal extCKE is kept at H level thereafter, in
clock cycles 14 and 15, remaining data Q2 and Q3 are read, respectively.
Therefore, in this data reading operation also, the data reading timing
from the SDRAM can be adjusted according to whether the CPU is ready to
receive data.
In addition to the structure providing a delay in the data input/output
timing, generation of the internal clock signal is stopped, and hence
internal clock signal intCLK can be constantly fixed at the L level by
fixing external clock signal extCKE at the L level continuously.
Therefore, the internal state of the SDRAM is not changed, and current
consumption can be reduced. Especially, taking of an external signal in
synchronization with external clock signal extCLK at the time of standby
can be stopped, change in the state of internal signals can be prevented,
and hence current consumption in the standby state can be reduced.
FIG. 17A shows an example of the structure of clock buffer 1 and internal
clock generating circuit 4 shown in FIG. 15. Referring to FIG. 17A, clock
buffer 1 includes an input buffer la for buffering external clock signal
extCLK, and an inverter 1b for inverting an output signal from buffer 1a.
A first internal clock signal intCLK0 is output from inverter 1b. An
internal clock signal intZCLK0 having complementary logic to external
clock signal extCLK is generated from buffer 1a.
Internal clock generating circuit 4 includes an NOR circuit 4a receiving
internal clock enable signal intCKE from CKE buffer 2 and internal clock
signal intZCLK0 from buffer 1a, and an inverter 4b inverting an output
signal from NOR circuit 4a'. From NOR circuit 4a', internal clock signal
intCLK as a second internal clock signal is output, and a complementary
internal clock signal intZCLK is output from inverter 4b.
FIG. 17B shows an example of a structure of CKE buffer 2 shown in FIG. 15.
Referring to FIG. 17B, CKE buffer 2 includes a buffer 2a buffering
external clock enable signal extCKE, a first latch circuit 2b for latching
and outputting an output signal from buffer 2a in synchronization with
internal clock signal intCLK0, and a second latch circuit 2c for latching
and outputting an output signal from the first latch circuit 2b in
synchronization with internal clock signal intZCLK0.
The first latch circuit 2b includes a tristate inverter 21a which is
selectively activated by internal clock signals intCLK0 and intZCLK0. The
tristate inverter 21a is activated when internal clock signal intCLK0 is
at the L level, and it inverts a signal applied from buffer 2a. When
internal clock signal intCLK0 is at the H level, the tristate inverter 21a
is inactivated and set to an output high impedance state.
The first latch circuit 2b further includes an inverter 21b receiving an
output signal from tristate inverter 21a, an inverter 21c for inverting
and transmitting an output signal from inverter 21b to an input portion of
inverter 21b, an inverter 21d receiving an output signal from inverter
21b, an NAND circuit 21e receiving internal clock signal intCLK0 and an
output signal from inverter 21d, an NAND circuit 21 receiving internal
clock signal intZCLK0 and an output signal from inverter 21b, an NAND
circuit 21g receiving at one input an output signal from NAND circuit 21e,
and an NAND circuit 21h receiving an output signal from NAND circuit 21f
and an output signal CKEO from NAND circuit 21g. An output signal from
NAND circuit 21h is applied to another input of NAND circuit 21e. NAND
circuits 21g and 21h constitute a flipflop.
The second latch circuit 2c includes an NAND circuit 22a receiving internal
clock signal intZCLK0 and an output signal CKE0 from NAND circuit 21g, an
NAND circuit 22b receiving internal clock signal intZCLK0 and an output
signal CKE0 from NAND circuit 21h, an NAND circuit 22c receiving at one
input an output signal from NAND circuit 22a, and an NAND circuit 22d
receiving an output signal from NAND circuit 22b and an output signal from
NAND circuit 22c for outputting a complementary internal clock enable
signal intZCKE. The internal clock enable signal intCKE output from NAND
circuit 22d is applied to another input of NAND circuit 22c. Internal
clock enable signal intZCKE is output from NAND circuit 22c. NAND gates
22c and 22d constitute a flipflop. The operations of the clock buffer and
the internal clock generating circuit shown in FIG. 17A as well as the
operation of the CKE buffer shown in FIG. 17B will be described with
reference to FIG. 18, which is a diagram of waveforms.
In clock cycle 0, when external clock signal extCLK rises to the H level
while the external clock enable signal extCKE is at the H level, internal
clock signal intZCLK0 from input buffer 1a of clock buffer 1 is set to the
L level, and the output signal from inverter 1b rises to the H level.
Meanwhile, in CKE buffer 2, the output signal from buffer 2a is at the L
level, as buffer 2a has an inverting function. In the first latch circuit
2b, the tristate inverter 21a is set to the output high impedance state in
response to the rise of internal clock signal intCLK0, and the H level
signal applied before the rise of internal clock signal intCLK0 is latched
by inverters 21b and 21c.
Each of NAND circuits 21e and 21f functions as an inverter in response to
the rise of internal clock signal intCLK0, and these circuits invert
signals applied from inverters 21d and 21b, and apply inverted signals to
NAND circuits 21g and 21h, respectively. In this state, the output signal
from NAND circuit 21e attains to the L level, and in response, the signal
CKE0 from NAND circuit 21g attains to the H level. In the second latch
circuit 2c, internal clock signal intZCLK0 falls to the L level.
Therefore, output signals from NAND circuits 22a and 22b attain to the H
level, and the second latch circuit 2c is set to a latch state in which a
signal applied before the fall of internal clock signal intZLK0 is
maintained. In this state, internal clock enable signal intCKE is at the H
level, while the complementary internal clock enable signal intZCKE is at
the L level. Therefore, in internal clock generating circuit 4, NOR
circuit 4a' functions as an inverter, and it inverts the signal applied
from buffer 1a of clock buffer 1 and generates internal clock signal
intCLK. The states of signals intCKE and intZCKE are defined in response
to the rise of internal clock signal intZCLK. Therefore, in clock cycle 0,
whether or not internal clock signal intCLK is generated is determined
dependent on the state of external clock enable signal extCKE of the
previous cycle.
In clock cycle 1, external clock enable signal extCKE is set to the L level
at the rising edge of external clock signal extCLK. In this state,
internal clock signal intCLK0 rises to the H level in accordance with
external clock signal extCLK, the first latch circuit 2b latches external
clock enable signal extCKE applied from buffer 2a and outputs the same.
Therefore, the output signal CKE0 from the first latch circuit 2b falls to
the L level in response to the rise of internal clock signal intCLK0.
Meanwhile, the second latch circuit 2c is at the latch state since
internal clock signal intZCLK0 is at the L level, and hence it keeps the
internal clock enable signal intCKE at the H level and the complementary
internal clock enable signal intZCKE at the L level.
Therefore, in clock cycle 1, NOR circuit 4a' functions as an inverter, and
in accordance with a signal from buffer 1a, internal clock signal intCLK
is generated. In clock cycle 1, when internal clock signal intCLK0
(external clock signal extCLK) falls to the L level, in the first latch
circuit 2b, tristate inverter 21a is activated, and it inverts the H level
signal from buffer 2a. However, NAND circuits 21d and 21f keep the output
signals therefrom at the H level because of the internal clock signal
intCLK0 at the L level, and hence the output states of NAND circuits 21g
and 21h are not changed. Therefore, the output signal CKE0 from the first
latch circuit 21b is kept at the L level. Meanwhile, the second latch
circuit is set to the through state in response to the rise of internal
clock signal intZCLK0, and it passes and latches the signal applied from
the first latch circuit 2b. In response, internal clock enable signal
intCKE attains to the L level, and the complementary internal clock enable
signal intZCKE attains to the H level.
As a result, in the internal clock generating circuit 4, the output signal
from NOR circuit 4a' is fixed at the L level, and internal clock signal
intCLK is fixed at the L level. The second latch circuit 2c maintains the
internal clock enable signal intCKE at the L level until the internal
clock signal intZCLK0 again rises to the H level (that is, until the
internal clock signal intCLK0 falls to the L level). Therefore, in clock
cycle 2, even if internal clock signal intCLK0 rises in accordance with
external clock signal extCLK, NOR circuit 4a' has its output signal fixed
at the L level, and rising (generation) of internal clock signal intCLK is
inhibited.
In clock cycle 2, when external clock enable signal extCKE is at the H
level, the first latch circuit 2b is set to the latch state in response to
the rise of internal clock signal intCLK0, and in accordance with the
signal at the H level taken in by that time, it returns the output signal
CKE0 to the H level.
Therefore, when the second latch circuit 2c is set to the through state in
response to the fall of internal clock signal intCLK0, internal clock
enable signal intCKE is set to the H level, and the complementary internal
clock signal intZCKE is set to the L level. Therefore, in clock cycle 3,
internal clock signal intCLK rises to the H level in accordance with the
rise of external clock signal extCLK.
As described above, in the first latch circuit 2b, the external clock
enable signal is latched and shifted in accordance with internal clock
signal intCLK0 and the output signal from the first latch circuit 2b is
shifted in the second latch circuit 2c in accordance with the internal
clock signal intZCLK0. Therefore, the internal clock enable signal intCKE
changes with a delay of a half cycle of external clock signal extCLK, and
the changed of state is maintained for 1 clock cycle. Accordingly, after
the fall of the internal clock signal intCLK, the internal clock signal
intCLK can be surely kept at the L level during the next clock cycle.
Further, the second latch circuit is released of the latch state and it is
set to the through state in response to the fall of internal clock signal
intCLK0. Therefore, when the external clock enable signal extCKE is set at
the H level, the internal clock signal intCLK can be surely kept at the
active state of H level in the next clock cycle.
As described above, the external clock enable signal extCKE is shifted
successively in accordance with the internal clock signal intCLK0 by first
and second latch circuits 2b and 2c. Therefore, when the external clock
enable signal extCKE is set to the L level indicating invalid state of the
external clock signal, in the next clock cycle, internal clock signal
intCLK can be surely fixed at the L level.
As the speed of operation of various semiconductor devices as components of
a system has been increased, new standard of interfaces have been proposed
so as to allow high speed signal propagation in the system. Such new
standards include GTL (Gunning Transceiver Logic), CTT (Center Tapped
Terminated), HSTL (High Speed Transceiver Logic) and SSTL (Stub Series
Terminated Logic or Stub Series Terminated Transceiver Logic). In these
interfaces, amplitude of an input signal is made smaller, time for
charging/discharging signal lines is made shorter so as to reduce power
consumption and to increase a speed of operation. For example, in HSTL and
CTT, the amplitude of an input signal is determined to be within the range
of reference voltage Vref .+-.0.2 V. Therefore, an input buffer provided
at a receiving side element must amplify the signal having such a small
amplitude. In these new standards, the H and L level amplitudes are
defined relative to the reference voltage, and hence an input buffer must
have a differential amplifying circuit.
FIG. 19 shows a structure of a first stage of a conventional input buffer.
Here, the first stage of an input buffer means a buffer circuit portion
directly receiving an external signal, which corresponds to buffer 1a or
2a.
Referring to FIG. 19, the input buffer of the first stage includes a p
channel MOS transistor PQ1 having one conduction node (source) connected
to a power supply node supplying power supply voltage Vdd and a gate and
another conduction node (drain) connected to a node N1; a p channel MOS
transistor PQ2 having one conduction node connected to the power supply
node, a gate connected to node N1 and another conduction node connected to
an output node N2; an n channel MOS transistor NQ1 having one conduction
node connected to a ground node supplying ground voltage Vss, a gate
connected to receive a reference voltage Vref and another conduction node
connected to node N1; and an n channel MOS transistor NQ2 having one
conduction node connected to the ground node, a gate connected to receive
an external signal EXT and another conduction node connected to output
node N2. In the structure of the input buffer of the first stage, p
channel MOS transistors PQ1 and PQ2 constitute a current mirror circuit.
External signal EXT may be any of externally applied control signals ZCS,
ZRAS, ZCAS and ZWE, address signal Add and write data D.
If the external signal EXT is higher than the reference potential Vref,
conductance of n channel MOS transistor NQ2 becomes larger than that of n
channel MOS transistor NQ1. MOS transistor NQ1 receives current from p
channel MOS transistor PQ1, and a current of the same magnitude as the
current flowing through p channel MOS transistor PQ1 flows through p
channel MOS transistor PQ2 (provided that MOS transistors PQ1 and PQ2 are
of the same size). Therefore, in this state, the current flowing through
MOS transistor PQ2 is all discharged to the ground node through MOS
transistor NQ2, and node N2 attains to the L level.
Meanwhile if the potential level of external signal EXT is lower than the
reference voltage Vref, conductance of n channel MOS transistor NQ1
becomes larger than that of MOS transistor NQ2. In this case, the current
flowing through p channel MOS transistor PQ2 becomes larger than the
current flowing through n channel MOS transistor NQ2, and the potential
level at node N2 is set to the H level.
By using such a differential amplifying circuit as shown in FIG. 19 in the
input buffer of the first stage, it becomes possible to generate an
internal signal ZOUT having large amplitude, by high speed amplification,
even when the external signal EXT has a small amplitude.
The reference voltage Vref is generally at the potential level of an
intermediate voltage (Vdd+Vss)/2 between the power supply voltage Vdd and
the ground voltage Vss. The amplitude of the external signal EXT is as
small as Vref .+-.0.2 (in case of HSTL and CTT interface: in GTL, it is
Vref .+-.0.05). However, even when the potential level of external signal
EXT is fixed at the level of the power supply voltage Vdd or of the ground
voltage Vss such as at the time of standby, the reference voltage Vref is
at the intermediate potential level, and hence in the differential
amplifying circuit, current always flows from the power supply node to the
ground node. More specifically, when the external signal EXT is at the
level of the power supply voltage Vdd, current flows to the ground node
through MOS transistor NQ2, and when the external signal EXT is at the
level of the ground voltage Vss, current flows to the ground node through
MOS transistor NQ1.
When the storage capacity of SDRAM increases, the number of input buffers
receiving the address signal bits will be increased, and if data of
multiple bits are to be input/output, the number of data input buffers
will be increased as well. Further, as the SDRAM comes to have many
functions, kinds of external control signals will be increased. Therefore,
when the number of external signals are increased in this manner, the
number of input buffers will be increased accordingly, and if such a
differential amplifier circuit as shown in FIG. 19 is used in the input
buffer of the first stage, the current constantly flowing through the
differential amplifying circuit becomes large, which hinders
implementation of an SDRAM having low current consumption.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a clock synchronous
semiconductor memory device which allows significant reduction in current
consumption by the input buffer.
Another object of the present invention is to provide a clock synchronous
semiconductor memory device which can surely reduce current consumption at
an input buffer without affecting access operation even when the external
clock signal has a high frequency.
The synchronous semiconductor memory device in accordance with the present
invention includes a clock buffer circuit generating a first internal
clock signal in accordance with an externally applied external clock
signal; a latch circuit latching an externally applied external clock
enable signal indicating validity of the external clock signal in
synchronization with the first internal clock signal for generating an
input buffer enable signal which is activated when the external clock
enable signal is active; a clock enable circuit for generating an internal
clock enable signal by providing a delay to the input buffer enable
signal; an internal clock generating circuit which is activated when the
internal clock enable signal is active, for generating a second internal
clock signal in accordance with the external clock signal; an input buffer
circuit which is activated when the input buffer enable signal is active,
for buffering an externally applied signal; and an internal signal
generating circuit for latching an output signal from the input buffer
circuit in synchronization with the second internal clock signal for
generating an internal signal.
The input buffer circuit includes a component which operates using voltages
on first and second power supply nodes as operational power supply
voltages, and for shutting off a current path between first and second
power supply nodes when the input buffer enable signal is inactive.
The external clock signal changes between first and second potential
levels. The latch circuit latches and outputs an externally applied
external clock enable signal indicating validity of the external clock
signal in synchronization with the change from the first potential level
to the second potential level of the first internal clock signal. The
internal signal generating circuit has substantially the same structure as
the latch circuit, and it latches the signal from the input buffer circuit
in response to a change from the first to the second potential level of
the second internal clock signal, and generates and outputs an internal
signal.
The input buffer enable signal is generated in response to external clock
enable signal in accordance with the first internal clock signal, and
current path of the input buffer circuit is shut off in accordance with
the input buffer enable signal. The input buffer enable signal is
generated in accordance with the external clock enable signal, and in the
cycle in which generation of the second internal clock signal is stopped,
the inside of the device is maintained at the state of the previous cycle.
Therefore, it is not necessary to take in an external signal. Therefore,
the input buffer circuit is set to the operative state only when
necessary, and current path of the input buffer circuit is shut off when
| | |
