A circuit for recovering a digital clock signal and a method therefor is disclosed. The digital clock recovery circuit includes an analog-to-digital (A/D) converter and asymmetry corrector for converting a received analog signal into digital data and providing corrected digital data corrected by a binarization level which traces the center value of the received signal, a frequency error detector for detecting a frequency error from the corrected digital data, a phase error detector for detecting a phase error from the corrected digital data, and a digital low pass filter (LPF) for providing the frequency error and the phase error as a control voltage. It is possible to trace the asymmetry of the received signal more sensitively than in the conventional technology by realizing an asymmetry corrector for correcting the asymmetry of the digital data which has undergone the analog-to-digital (A/D) conversion, the phase error detector, and the LPF by a digital circuit, thus generating a system clock signal and to improve the reliability of the system by stably generating the system clock signal.

A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency f.sub.REF and the synthesized output frequency signal f.sub.VCO is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency f.sub.REF to be greater than the channel spacing, i.e., the channel spacing can be smaller than the reference frequency f.sub.REF. Thus, a much quicker settling time and improved VCO phase noise are provided, either of which results in a significant improvement in the performance of virtually any communications system.

According to some embodiments, a charge pump includes a first transistor to steer an amount of current to a second transistor coupled to the first transistor in a first folded cascode arrangement and to a current mirror to sink substantially the amount of current from a load, and a third transistor to steer the amount of current to a fourth transistor coupled to the third transistor in a second folded cascode arrangement to source substantially the amount of current to the load.

A PLL circuit includes a phase comparator; a charge pump; a loop filter; a voltage-controlled oscillator; a frequency dividing circuit; an A counter for dividing the P-frequency-divided output; circuits for generating two signals, which have a phase difference equivalent to one period of the P-frequency-divided output of the frequency dividing circuit; and an interpolator for producing an output signal obtained by interpolating the phase difference between the two signals in accordance with an interior division ratio. The interpolator interpolates in steps of a value obtained by dividing the phase difference by P and incrementing or decrementing a value B, which decides an interior division ratio B:P-B, by B whenever frequency-division by A is performed, and a control circuit. The phase of the output of the interpolator is fed to the phase comparator and compared with the phase of a reference clock, and divides by a frequency-dividing factor.

A phase detector circuit includes a first flip flop, a second flip flop, a first charge pump and a second charge pump. Outputs of the flip flops directly enable the charge pumps in response to received clocking signals. A first delay circuit delays the output signal from the first flip flop to an AND gate which combines the delayed output signal and the output signal from the second flip flop. The AND gate output is delayed in a second delay circuit to produce a delayed reset signal which resets both flip flops simultaneously and disables the charge pumps. The phase detector circuit balances the amount of charge provided to a phase locked loop near the in-phase condition to improve linearization of the phase detector.