Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation

What is claimed is:

1. An integrated circuit comprising:

an embedded core for executing computer instructions at an operational clock period;

logic within the integrated circuit and coupled to the embedded core; and

a plurality of speed path testing cells coupled to the embedded core wherein the speed path testing cells in the plurality of speed path testing cells allow the embedded core to be speed path tested by a launch event and a capture event which are separated in time by a time period which is equal to or less than the operational clock period wherein the embedded core contains at least one serial scan chain of serially coupled storage elements and the plurality of speed path testing cells being coupled in another serial scan chain.

2. The integrated circuit of claim 1 wherein speed path testing is performed by providing a first clock cycle to launch a logical signal transition as the launch event through a circuit path and providing a second clock cycle to capture speed path test results as the capture event.

3. The integrated circuit of claim 1 wherein the embedded core is controlled by a system clock and the plurality of speed path testing cells are controlled by a test clock.

4. The integrated circuit of claim 1 wherein the at least one serial scan chain of serially coupled storage elements is coupled to the another serial scan chain of the plurality of speed path testing cells.

5. The integrated circuit of claim 1 wherein the logic within the integrated circuit contains at least one serial scan chain of serially coupled storage elements and the plurality of speed path testing cells being coupled in another serial scan chain.

6. The integrated circuit of claim 1 wherein the plurality of speed path testing cells perform the capture event by storing incoming data bits.

7. The integrated circuit of claim 1 wherein the plurality of speed path testing cells perform the launch event by creating a logical transition through a circuit path within the integrated circuit.

8. The integrated circuit of claim 1 wherein the plurality of speed path testing cells perform speed path testing of the logic within the integrated circuit.

9. The integrated circuit of claim 1 wherein the plurality of speed path testing cells perform speed path testing of the embedded core.

10. The integrated circuit of claim 1 wherein at least one of the speed path testing cells within the plurality of speed path testing cells comprises:

a multiplexor having an output coupled to the embedded core, a first input coupled to the logic within the integrated circuit, and a second input; and

at least one storage element having an input coupled to received scan test data and an output coupled to the second input of the multiplexor.

11. The integrated circuit of claim 10 wherein the at least one storage element comprises:

a first flip-flop having a scan data input coupled to another speed path testing cell and an output; and

a second flip-flop having a data input coupled to the output of the first flip-flop and an output coupled to the multiplexor.

12. The integrated circuit of claim 1 wherein at least one of the speed path testing cells within the plurality of speed path testing cells comprises:

a multiplexor having an output coupled to the logic within the integrated circuit, a first input coupled to the embedded core, and a second input; and

at least one storage element having an input coupled to received scan test data and an output coupled to the second input of the multiplexor.

13. The integrated circuit of claim 12 wherein the at least one storage element comprises:

a first flip-flop having a scan data input coupled to another speed path testing cell and an output; and

a second flip-flop having a data input coupled to the output of the first flip-flop and an output coupled to the multiplexor.

14. The integrated circuit of claim 1 wherein at least one of the speed path testing cells within the plurality of speed path testing cells comprises:

a first multiplexor having an output coupled to the embedded core, a first input coupled to the logic within the integrated circuit, and a second input;

at least one storage element having an input coupled to receive scan test data and an output coupled to the second input of the first multiplexor; and

a second multiplexor having an output coupled to the logic within the integrated circuit, a first input coupled to the embedded core, and a second input coupled to the output of the at least one storage element.

15. The integrated circuit of claim 14 further comprising:

a third multiplexor having an output coupled to a data input of the at least one storage element, a first input coupled to an output of the embedded core, and a second input coupled to an output of the logic within the integrated circuit.

16. The integrated circuit of claim 14 wherein the at least one storage element comprises:

a first flip-flop having a scan data input coupled to another speed path testing cell and an output; and

a second flip-flop having a data input coupled to the output of the first flip-flop and an output coupled to the second input of the first multiplexor and the second input of the second multiplexor.

17. The integrated circuit of claim 1 wherein at least one of the speed path testing cells within the plurality of speed path testing cells comprises:

a multiplexor having an output coupled to the embedded core, a first input coupled to the logic within the integrated circuit, a second input coupled to perform speed path testing, and a third input coupled to provide serial test data to the embedded core.

18. The integrated circuit of claim 1 wherein at least one of the speed path testing cells within the plurality of speed path testing cells comprises:

a multiplexor having an output coupled to the logic within the integrated circuit, a first input coupled to the embedded core, a second input coupled to perform speed path testing, and a third input coupled to provide serial test data to the logic within the integrated circuit.

19. An embedded core for use within an integrated circuit, the embedded core comprising:

a data processor portion coupled to a system clock; and

a plurality of speed path test cells coupled to the data processor portion to enable speed path testing of the data processor portion, wherein each speed path test cell within the plurality of speed path test cells comprises:

a multiplexor having an output coupled to an input of the data processor portion, a first input coupled to receive normal mode data, and a second input for receiving speed path testing data;

a first storage element having an output coupled to the second input of the multiplexor, a data input, and a clock input for receiving a test clock that is different from the system clock; and

a second storage element having an output coupled to the data input of the first storage element, a serial data input for receiving serial scan data, and a clock input for receiving a test clock that is different from the system clock, whereby the plurality of speed path test cells provide a logic transition to a circuit path within the data processor portion to test a signal propagation time through the circuit path.

20. The embedded core of claim 19 wherein the plurality of speed path test cells are used to determine a set-up time of the input of the embedded core.

21. The embedded core of claim 19 wherein the plurality of speed path test cells are used to determine a hold time of the input of the embedded core.

22. An embedded core for use within an integrated circuit, the embedded core comprising:

a data processor portion coupled to a system clock; and

a plurality of speed path test cells coupled to the data processor portion to enable speed path testing of the data processor portion, wherein each speed path test cell within the plurality of speed path test cells comprises:

a first multiplexor having an output, a first input coupled to receive normal mode data from an output of the data processor portion, and a second input;

a first storage element having an output coupled to the second input of the first multiplexor, a data input, and a clock input for receiving a test clock that is different from the system clock; and

a second storage element having an output coupled to the data input of the first storage element, a serial data input for receiving serial scan data, and a clock input for receiving a test clock that is different from the system clock, whereby the plurality of speed path test cells perform a capture operation for data provided from an output of the data processor portion so that a circuit path within the data processor portion is speed path tested.

23. The embedded core of claim 22 wherein the plurality of speed path test cells are used to determine a clock-to-output-valid time of the output of the embedded core.

24. The embedded core of claim 22 wherein the plurality of speed path test cells are used to determine a output hold time of the output of the embedded core.

25. An embedded core for use within an integrated circuit, the embedded core comprising:

a data processor portion coupled to a system clock; and

a plurality of speed path test cells coupled to the data processor portion to enable speed path testing of the data processor portion, wherein each speed path test cell within the plurality of speed path test cells comprises:

a multiplexor having an output coupled to the data processor portion, a first input coupled to receive normal mode data from an output of the data processor portion, and a second input for receiving speed path testing data;

a first storage element having an output coupled to the second input of the multiplexor, a data input, and a clock input for receiving a test clock that is different from the system clock;

a second storage element having an output coupled to the data input of the first storage element, a serial data input for receiving serial scan data, and a clock input for receiving a test clock that is different from the system clock; and

a second multiplexor having an output, a first input coupled to an output of the data processor portion, and a second input coupled to the output of the first storage element.

26. The embedded core of claim 25 wherein each speed path test cell within the plurality of speed path test cells comprises:

a third multiplexor having a first input, a second input coupled to the first input of the second multiplexor, and an output coupled to a data input of second storage element.

27. The embedded core of claim 25 wherein each speed path test cell within the plurality of speed path test cells: (1) generates speed path test transitions to test a speed path within the data processor portion; and (2) captures test outputs from the data processor portion based upon multiplexor settings.

28. An integrated circuit comprising:

an embedded core for executing computer instructions at an operational clock period defined by a system clock;

logic within the integrated circuit and coupled to the embedded core; and

a plurality of speed path testing cells coupled to the embedded core wherein the plurality of speed path testing cells are coupled to a test clock whereby the system clock initiates a function of either a speed path transition launch or a speed path data capture and the test clock initiates a function opposite of the function enabled by the system clock so that a circuit path within the integrated circuit is speed path tested.

29. A method for speed path testing an embedded core within an integrated circuit, the method comprising the steps of:

providing the integrated circuit, the integrated circuit containing the embedded core and microcontroller logic coupled to the embedded core, the integrated circuit containing a plurality of speed path test cells coupled to the embedded core;

serially shifting data into at least one scan chain within the embedded core;

serially shifting data into a test scan chain which serially couples each speed path test cell in the plurality of speed path test cells, the step of serially shifting data into the test scan chain being performed in parallel with the step of serially shifting data into the at least one scan chain; and

speed path testing the embedded core using test data provided from the test scan chain.

30. The method of claim 29 wherein the step of speed path testing tests hold time, the step of speed path testing comprising the steps of:

providing a system clock edge on a system clock; and

providing a test clock edge on a test clock wherein the test clock edge results in data being changed to an input to the embedded core, the test clock edge being timed so that the data changes logic state at an interval later than the system clock edge, this interval being substantially equal to a hold time specification of the input to the embedded core.

31. The method of claim 29 wherein the step of speed path testing tests set-up time, the step of speed path testing comprising the steps of:

providing a system clock edge on a system clock; and

providing a test clock edge on a test clock wherein the test clock edge results in data being changed to an input to the embedded core, the test clock edge being timed so that the data changes logic state at an interval earlier than the system clock edge, this interval being substantially equal to a set-up time specification of the input to the embedded core.

32. A method for speed path testing an embedded core within an integrated circuit, the method comprising the steps of:

providing the integrated circuit, the integrated circuit containing the embedded core and microcontroller logic coupled to the embedded core, the integrated circuit containing a plurality of speed path test cells coupled to the embedded core;

serially shifting data into at least one scan chain within the embedded core;

serially shifting data into a test scan chain which serially couples each speed path test cell in the plurality of speed path test cells, the step of serially shifting data into the test scan chain being performed in parallel with the step of serially shifting data into the at least one scan chain; and

speed path testing the embedded core by capturing test data within the test scan chain wherein the test data is provided as output from the embedded core.

33. The method of claim 32 wherein the step of speed path testing performs clock-to-output-valid testing, the step of speed path testing comprising the steps of:

providing a system clock edge on a system clock, this system clock edge causing data on an output of the embedded core to be changed in logic state; and

providing a test clock edge on a test clock wherein the test clock edge results in data being sampled at an output of the embedded core, the test clock edge being timed so that the data is sampled at an interval later than an edge provided on the system clock, this interval being substantially equal to a clock-to-output-valid specification of the output of the embedded core.

34. The method of claim 32 wherein the step of speed path testing tests output hold time, the step of speed path testing comprising the steps of:

providing a system clock edge on a system clock, this system clock edge causing data on an output of the embedded core to be changed in logic state; and

providing a test clock edge on a test clock wherein the test clock edge results in data being sampled at an output of the embedded core, the test clock edge being timed so that the data is sampled at an interval later than an edge provided on the system clock, this interval being substantially equal to an output hold time specification of the output of the embedded core.

35. An embedded core integrated into a microcontroller, the embedded core comprising:

a processor portion containing a first plurality of storage elements which perform normal mode operations within the processor portion, the processor portion being adapted to receive a clock signal from a first clock source, the first plurality of storage elements coupled into a first scan chain; and

a wrapper portion containing a second plurality of storage elements which do not perform normal mode operations within the processor portion but are used for testing the processor portion, the wrapper portion being adapted to receive a clock signal from a second clock source different from the first clock source, the second plurality of storage elements coupled into a second scan chain.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates generally to testing of integrated circuits, and more particularly to, speed path testing of conductive paths in an integrated circuit containing an embedded core central processing unit (CPU).

BACKGROUND OF THE INVENTION

In the modern integrated circuit industry, there is a class of integrated circuits known as microcontrollers or "system-on-a-chip" devices. These devices are manufactured and designed to contain embedded core data processors wherein this embedded core communicates with peripherals, memory, or other circuitry on the same substrate. The embedded core may be designed and/or provided by the integrated circuit (IC) manufacturer, or may be designed and/or provided by a third party (not the customer or the integrated circuit manufacturer), whereas the peripherals and other circuitry is typically customer specific. In many cases, the customer specific material is provided and/or designed by a different party from that which designed/provided the embedded core. Therefore, testing of integrated circuits is made increasingly difficult due to the many parties and design/test methodologies that may be involved in the design as well as the inaccessibility of circuit elements embedded deep within a microcontroller design. As more embedded core processors, or "system-on-a-chip" devices are designed, or as the level of integration increases such that many embedded cores from many providers are included on a single device, new test methods must be used.

The embedded core, which is only a portion of the total integrated circuit (IC) and is surrounded by peripherals, typically contains a plurality of input and output terminals. If the embedded core is kept as a separate structure during test pattern generation and is not bundled together with the rest of the integrated circuit logic for test pattern generation, then there is an access problem (controllability and observability) related to these plurality of input and output terminals (e.g., the input and output terminals used to test the embedded core are not accessible by the microcontroller external terminals or package pins). In most cases, the plurality of input and output terminals of the embedded core are not directly accessible by the external pins of the integrated circuit, and therefore, no direct access is available to the embedded core for providing test vectors or for other test purposes.

In addition, the complexity and transistor count of integrated circuits (ICs) has significantly increased so that simple connectivity testing and stuck-at fault testing is not adequate for modern microcontrollers. It is important that the embedded core be tested for frequency compliance, input and output terminal timing specification compliance, manufacturing induced path delay faults and transition delay faults, in addition to stuck-at faults and connectivity. It is even more advantageous if the speed path verification tasks can be performed at the operational frequency of the embedded core.

One prior art method for overcoming these design and access difficulties to the embedded core is to provide a signal path between every input terminal and every output terminal of the embedded core and a different external pin of the integrated circuit. This architecture, commonly known as "multiplexor mode", creates significant overhead in the design. In addition, routing of the signal path for "multiplexor mode" may not be possible since the number of input/output terminals on the embedded core may exceed the number of external pins of the integrated circuit (IC). In addition, this method of signal path routing can complicate the testing of the timing of the inputs and outputs to the embedded core. Furthermore, this method can result in a lower quality test program, an impact to the device die area, or an impact to the design schedule (i.e., being late to market with microcontroller design derivatives). For example, to conduct a reasonable speed or timing test would require that each signal path connection for the device package pins to the embedded core inputs and outputs be fully characterized at each operating point (temperature and supply voltage) at which the device is to be tested. This characterization will never result in a fixed propagation delay along such a signal path, but will always provide a range of possible values for that propagation delay (minimum and maximum) due to process variation in the manufacture of such products. The magnitude of the range from the minimum to maximum propagation delay for each of these signals introduces an uncertainty into the measurement or validation of embedded core input and output specifications along such propagation paths. This additional uncertainty leads to either a reduced test quality, yield reduction, or both.

Another method for overcoming the design and access difficulties is to provide a wholly serial connection whereby the embedded core input and output terminals are provided data, or are interrogated for data, respectively, by using a common-in-the-art serial scan connections. This method has the drawback of increasing test time unreasonably and not allowing at-speed testing to occur. For example, an embedded core with 100 input terminals and 100 output terminals would require 200 clock cycles to provide and interrogate one data processor cycle of terminal data. A vector set with 1000 data processor clock cycles worth of test data would be extended or multiplied by 200 and would result in an actual applied clock cost of 200,000 clock cycles. The effective frequency tested would also be reduced by 200 so a 200 MHz data processor would effectively be tested at 1 MHz.

In another prior art method, the embedded core and associated peripherals can be placed on a single chip and modeled together in such a way that the whole chip design is considered as a single entity where the embedded controller is not individually testable. For this type of design the test vectors are generated for the entire integrated circuit (IC) whereby the hierarchy of the sub-components of the microcontroller are ignored. This method is typically time inefficient since each and every integrated circuit which contains the same embedded core must be separately processed to create new test vectors whereby existing or old embedded test vectors must be discarded. This design process is generally not supported in the industry due to the intellectual property content of the embedded core data processor or of the customer supplied logic. Most suppliers of embedded cores and peripherals do not desire to disclose extensive details of there designs thereby rendering new generation of test vectors very difficult after full integration.

It would be advantageous to generate an initial set of test vectors when designing the embedded core and provide a method and system to allow the use of these initial test vectors to perform testing on the embedded core regardless of which peripherals are integrated with the embedded core. It would be advantageous to provide a method which would decouple the embedded core test process from customer specific designs and peripherals which may be located on the same substrate with the embedded core. A new isolated embedded core test process is needed since most customer specific designs use different test methodologies from that originally designed into the embedded core and may contain proprietary information which cannot be communicated to the manufacturer of the embedded core. In addition, it is important that the substrate surface area overhead associated with this embedded core test circuitry be minimized.

Therefore, the need exists for a method and system which allows for speed path and at-speed testing of embedded core designs whereby test vectors can be reused and access to the embedded core is enabled in a substrate-space efficient manner.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in a block diagram, an integrated circuit containing speed path test cells for testing an embedded core in accordance with the present invention.

FIG. 2 illustrates, in a block diagram, another system containing speed path test cells which enable the testing of an embedded core in accordance with the present invention.

FIG. 3 illustrates, in a block diagram, yet another system which enables testing of an embedded core.

FIG. 4 illustrates, a circuit schematic, timing delays associated with using a wrapper cell to test timing specification for an embedded core input port in accordance with the present invention.

FIG. 5 illustrates, a circuit schematic, timing delays associated with using a wrapper cell to test timing specification for an embedded core output port in accordance with the present invention.

FIG. 6 illustrates, a circuit schematic, a measurement circuit which allows for measurement of the skew between two clock signals and other circuit characteristics in accordance with the present invention.

FIG. 7 illustrates, a circuit schematic, a measurement circuit which allows for measurement of the skew between two clock signals and input set-up circuit characteristics in accordance with the present invention.

FIG. 8 illustrates, a circuit schematic, a measurement circuit which allows for measurement of the skew between two clock signals in accordance with the present invention.

It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the FIGURES have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the FIGURES to indicate corresponding or analogous elements.

Description of a Preferred Embodiment

Overview

Generally, the present invention is a method and system for testing an embedded core data processor within an integrated circuit (IC). In order to allow for speed path testing (also referred to as critical path testing), logic transition delay testing, and similar at-speed testing, a set of wrapper cells or plurality of speed path test cells are provided around a periphery of the embedded core. The plurality of speed path test cells are coupled to the inputs and outputs of the embedded core and may also interface to peripheral circuitry and other logic integrated onto the same substrate with the embedded core. Therefore, the plurality of speed path test cells allow access to the otherwise inaccessible inputs and outputs of the embedded core to enable speed path testing and like at-speed testing of the embedded core. It must also be noted that the plurality of speed path test cells also allow speed path testing of the peripheral and other integrated logic that interfaces to the embedded terminals of the embedded data processor (since these terminals are equally inaccessible in the absence of a test structure).

In addition, the test vectors created when the embedded core was designed are capable of testing the embedded core regardless of how the embedded core is subsequently integrated with any other customer specific logic or on-chip peripherals. It is advantageous that the same test vectors are applicable for any microcontroller derivative product which is subsequently designed to contain the embedded core since it saves time, avoids proprietary disclosure, and enables the rapid development of derivative products containing the same core. The overhead substrate surface area of the plurality of speed path test cells is minimal. In addition, the plurality of speed path test cells may provide at-speed test capability for customer specific on-chip portions.

Manufacturing tests for any integrated circuit (IC) device should ideally ensure that there exist no manufacturing-induced defects that either: (1) prevent the device from performing the functions that it is specified to perform in the functional or operational specification; or (2) prevent the device from meeting all its functional timing specifications. The prior art method for high-quality tests to meet these two requirements are to fully scan all sequential elements in the design, and use automatic test pattern generation (ATPG) software to generate stuck-at, transition delay, and path delay patterns for the entire integrated circuit. However, if one hundred microcontrollers are designed using the same embedded core, then one hundred different sets of test vectors must be generated and maintained to test the one hundred different microcontrollers.

The present invention enables the testing of embedded cores without the need for performing ATPG every time the embedded core is integrated into a new microcontroller design. Embedded cores are groups of logic that are reused in multiple different microcontroller designs. Any one embedded core is integrated either alone or with other cores onto an integrated circuit (IC) which contains other logic to perform other specific functions unique to each microcontroller. In some cases, the logic provided on the same substrate with the embedded core is customer-designed and the details of this design are not provided to the embedded core designer. The design methodology and test strategy used by the customer for the logic external to the core may be entirely different from that employed in the embedded core. Because the logic surrounding the core is different from one application to the next, it is desirable to insulate the embedded core from the surrounding logic so that test patterns can be developed for that core and reapplied without the need for significant change for each new application of the embedded core. Also, it is not always possible to require that the customer-specified logic surrounding the embedded core be fully scanned via scan chain designs. Most customer designs and simpler peripherals are not held to higher scan design standards of embedded cores and required to do all of stuck-at, transition delay, and path delay testing which is required for modern embedded cores. In such cases, the controllability of input signals to the core and observability of output signals from the core, both of which are required to produce high-quality tests for the embedded core, are lacking when not using the devices taught in FIGS. 1-3.

When performing speed path testing, a logic transition is "launched" at a start of a circuit path and speed path test data is "captured" at the end of the circuit path. Therefore, a speed path test is a two-clock-edge test. One clock edge performing the "launch" and another clock edge performing the "capture". In some cases, a clock edge of a first clock signal performs the "launch" where a clock edge of a second clock signal performs the "capture". In other cases, the same clock enables both "launches" and "captures" via two sequential edges.

"Launching a transition" on an input to a cone of combinational logic is the application of a 0.fwdarw.1 transition or 1.fwdarw.0 transition on an input terminal of a circuit path. It is desirable, though not absolutely necessary, to apply the transition while holding all other inputs to the cone of logic at a constant (unchanging) logic value so that the speed path in question is not adversely logically affected by logic fluctuations on adjacent circuit paths. When all "off-path" values involved with the circuit path are held stable, the test is known as a "robust" test, and much less likely to be corrupted. Note that multiple timing paths may be robustly tested concurrently if their respective logic cones are disjoint. This concurrent multiple path test would be done by launching transitions on the input terminals of each path while holding other inputs to each of the logic cones constant. In order to test input timing specifications for the embedded core, the design is able to launch (on a first clock event) transitions onto core inputs. These transitions then propagate through zero or more combinational logic gates and the resulting data values at the path endpoints are captured (on a second clock event) into a state element (latch or flip-flop) within the embedded core. The transition should be launched with appropriate timing such that the input has an interval of time in which to propagate and be captured, and that interval should not exceed the length of the worst-case timing specification for that input. Since input timing specifications vary from one port on the core to the next, there is a need to launch