A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.
A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.
A semiconductor device, having a contact pad grown by an anisotropical silicon selective growth technique, includes a first word line crossing a diffusion layer formed on a substrate and surrounded by an element separating region at a right angle, a second word line parallel with the first word line formed over a rounded corner of the diffusion layer, and an area of the diffusion layer rectangularly partitioned by the first and second word lines. So that anisotropical silicon selective epitaxial growth from this area of the diffusion layer is achieved, avoiding isotropical growth deteriorated by the rounded corner.
On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug. As a result, increase in leakage at the junction of the diffusion layer is prevented by the low-resistance contact plug including the silicon-germanium alloy.
A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.
A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.
