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Description  |
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FIELD OF THE INVENTION
The invention described herein relates to processing systems for digitized
video signals and, in particular, to a multi-function device for
manipulating compressed video sequences, to be used as an aid in encoding
and decoding those sequences. Hereinafter, reference will be made, by way
of non-limiting example, to sequences arranged in accordance with
international standard ISO/IEC 13818-2 (also known as ISO/MPEG2), but the
invention can be applied to sequences encoded and decoded according to
principles similar to those disclosed in the standard. For the sake of
simplicity, those sequences shall hereinafter be referred to as MPEG2
video sequences or data.
BACKGROUND OF THE INVENTION
As is well known, the standard specifies the encoded (or compressed)
representation of video sequences for digital storage and digital video
communications and defines the decoding process. The encoding process is
not defined in the standard, and it is essentially a hybrid coding, using
time prediction techniques with motion estimation (at the pixel block
level) to reduce time redundancy, and two-dimensional transform techniques
applied to a current picture or to the significant differences between the
current picture and a predicted picture to reduce spatial redundancy.
Information on the encoding procedures (e.g. with or without prediction
and/or motion compensation), motion information and spatial information
are then transmitted after encoding with a variable length code. Decoding
entails processing the compressed sequences in successive steps, until the
original picture sequence is recovered for its subsequent display. In
particular, after decoding the variable length code and re-ordering the
transmitted coefficients, the latter are subjected to inverse
quantization, and spatial and time redundancies are re-introduced. Greater
detail can be found in the standard mentioned above as well as in standard
ISO/IEC 11172-2 (ISO/MPEG1) and in the paper "The MPEG video compression
algorithm", by D. J. Le Gall, Signal Processing: Picture Communication,
Vol. 4, No. 2, pp. 129 et seq.
Several devices for encoding and/or decoding MPEG2 video sequences are
commercially available. These devices perform all of the functions of an
encoder or decoder in accordance with the standard. In general, however,
such devices are not meant for professional use (i.e. for use by a
television broadcaster or by producers of video disks or compact disks)
but rather for "home" users: hence, they only allow pre-set and limited
variations of the encoding parameters, and the quality of the encoded or
decoded signals they provide is sufficient only if the signals have not
been subjected to particular manipulations (e.g. a succession of encoding
and decoding operations, as may occur in a television transmission). In
general, it is not possible to manipulate these parameters through a
control processing unit. To obtain the high encoding quality required for
professional use, the possibility of acting on several encoding and
decoding parameters at different stages of their respective processes must
be provided for this entails the introduction of arrays of discrete
components in the different parts of the equipment, which results in
larger equipment size and higher costs.
OBJECT OF THE INVENTION
It is an object of the invention to provide a device which can be used to
accomplish several of the operations required of a professional quality
MPEG2 video transmitter or receiver, thereby contributing to reducing its
size and offering remarkable performance in terms of function and speed.
SUMMARY OF THE INVENTION
The device according to the invention comprises, in a single integrated
circuit:
a first memory system for temporarily storing and formatting the sequences
to be manipulated, before forwarding them to an external memory or to the
output of the device;
a second memory system, for temporarily storing and formatting sequences
read from the external memory, before forwarding them to the output of the
device;
addressing means for writing sequences into the external memory or reading
sequences from the external memory;
means for processing data read from the external memory;
means for receiving, decoding and sending to the other units of the device
parameters containing information about the manipulations to be performed
on the sequences received or on the sequences to be transmitted;
means for organizing the data to be emitted into a format required by a
particular function to be performed; and
means for configuring the device in order to make it operate in one of a
plurality of modes, each corresponding to a different function.
According to a preferred embodiment of the invention, the configuration
means make the device operate so as to allow its use, in a transmission
and reception system, as:
device for re-ordering sequences from an acquisition order to an encoding
order at the transmission side or, conversely from an encoding order to a
display order at the reception side, by using the external memory, such
re-ordering requiring a conversion from a raster scan format to a
macro-block scan format or the reverse, and possibly a conversion between
two different raster scan formats;
a device for scan format conversion from a macro-block scan format to a
block scan format or vice versa, upstream of circuits computing a
two-dimensional transform or downstream of circuits computing an inverse
transform, such conversion using the first memory system alone; and
prediction device for generating predicted pictures, possibly with motion
compensation, starting from one or more reference pictures stored in the
external memory, such generation requiring extracting, from the external
memory, macro-blocks to which motion vectors may be applied, with regard
to both luminance pixels and chrominance pixels, or extracting sets of
luminance or chrominance pixels of pre-defined size, larger than that of a
macro-block.
BRIEF DESCRIPTION OF THE DRAWING
The above and other objects, features, and advantages will become more
readily apparent from the following description, reference being made to
the accompanying drawing in which:
FIG. 1 is a simplified functional diagram of an MPEG-2 video sequence
transmitter;
FIG. 2 is a simplified functional diagram of the receiver;
FIG. 3 is a diagram depicting the inputs, the outputs and the connections
to the external memory of the device according to the invention;
FIGS. 4A-4D are diagrams showing pixel arrangement in the external memory;
FIG. 5 is a block diagram of the device according to the invention;
FIGS. 6A-9 are more detailed diagrams of some blocks shown in FIG. 5; and
FIGS. 10A and 10B are diagrams showing some synchronism signals concerning
the output interface.
SPECIFIC DESCRIPTION
Before describing the Figures in detail, it is worthwhile to recall some
definitions concerning the hierarchical arrangement within a digitized
picture and the encoding modes at the picture level. Both luminance and
chrominance samples (pixels) are grouped into blocks each in an 8.times.8
matrix (8 rows of 8 pixels each), and a certain number of luminance and
chrominance blocks (e.g. 4 blocks of luminance data and 2 corresponding
blocks of chrominance data) form a macro-block. The picture is then formed
by a matrix of 36.times.45 or 30.times.45 macro-blocks (depending on
whether the power supply frequency is 50 or 60 Hz). Pictures can in turn
have a frame structure (in which pixels of subsequent rows pertain to
different fields) or a field structure (in which all pixels pertain to the
same field). As a consequence, macro-blocks may have a frame or field
structure, as well.
With regard to encoding modes, the following types of encoded pictures can
be recognized:
pictures subjected to intra-picture encoding (I pictures), i.e. pictures
encoded using only information contained within them;
pictures encoded with prediction (P pictures), i.e. pictures for which the
difference between the current picture and a picture obtained by means of
a prediction with motion compensation starting from one or more past
reference pictures is encoded; and
pictures encoded with bi-directional prediction (B pictures), i.e. pictures
encoded by using a prediction with motion compensation starting from past
and/or future reference pictures.
A reference picture is a reconstructed (decoded) picture, which had been
encoded as an I or a P picture.
This stated, the transmitter (FIG. 1) receives from a source, not
represented here, digital samples arranged according to the hierarchical
structure described above, present on a line 1. The succession of samples
is fed to a motion estimation unit SM which determines the type of
encoding for the current picture and computes and emits, if necessary, one
or more motion vectors representing the displacement between the position
of a macro-block in the current picture and its position in the reference
picture or pictures. Then, a sequence re-ordering unit RS converts the
order of the pictures from the one in which the pictures are emitted by
the source (acquisition and display order) into an order (encoding order)
suitable for the encoding type (in particular, an order allowing to decode
the reference pictures before the predicted pictures). The re-ordered
sequence is fed to the actual encoding (or compression) units, indicated
in the whole by COD. At the input of COD, a subtractor ST subtracts, in
case of P and B pictures, the reference picture or pictures (predicted and
stored in a circuit P1) from the current picture and feeds the difference
to a circuit CS for scan conversion from the macro-block format to the
block format, as required to compute the two-dimensional transform.
References T, Q indicate the circuits for computing the transform (in
particular, a discrete-cosine transform) and quantizing the transform
coefficients. The coefficients to be used are fed on one hand to the local
decoder for reconstructing the reference picture or pictures, and on the
other hand to an encoder CV which encodes them according to a variable
length code. CV sends the encoded coefficients, through a line 2, to a
receiver or to a memory device together with the motion vector or vectors
and with information on the encoding type. The local decoder comprises an
inverse quantizer 1Q1, a circuit IT1 for computing the inverse transform
and a circuit ICS1 for reconverting the scan format from the block format
to the macro-block format. The output signal from ICS1 is added in an
adder SM1 with the predicted reference picture, stored in P1 and suitably
delayed in a delay element RIT1. The result is fed to P1 for the new
prediction.
For the sake of simplicity, the drawing does not show the means which
combine the quantized and encoded coefficients of the transform with the
information emitted by motion estimator SM and which arrange the bit
stream of the encoded signal according to the syntax established by the
standard. The detailed description of that syntax is immaterial for the
purposes of the present invention.
In FIG. 2 the receiver comprises, downstream of the units (not represented)
which extract the different kinds of information from the bit stream
present on a line 3, decoder DEC in turn comprising circuit ICV for
decoding the coefficients encoded according to the variable length code,
and circuits IQ2, 1T2, ICS2, SM2, P2, RIT2, similar to circuits IQ1, IT1,
ICS1, SM1, P1, RIT1 shown in FIG. 1. The reconstructed pictures, in the
encoding order, are present at the output from SM2 and are then fed to
circuit IRS which performs the inverse operation with respect to RS (FIG.
1) re-establishing the display order before forwarding the pictures to
utilization devices through a line 4.
Blocks RS, IRS and P1, P2 also incorporate the external memories needed for
the blocks themselves to operate. Note also that FIGS. 1 and 2 depict
solely the data flow.
The device according to the invention can be used to build each one of the
blocks RS, CS, ICS1, P1 in FIG. 1 and blocks ICS2, P2, IRS in FIG. 2.
Hence, it can perform the following main functions:
1) Reordering picture sequences from the acquisition order to the encoding
order and vice versa. This operation entails converting picture format
from a "raster scan" format to a format known as Progressive Macro-Block
Scan (PMBS) format: the latter term means that, for luminance, the 16
pixels of a row of the macro-block are read before moving on to the next
row, whereas, for chrominance, pixel pairs Cb, Cr are read in sequence.
For the sake of simplicity, hereafter, the term "progressive macro-block"
or just "macro-block" shall be used to indicate that format. Re-ordering
can be performed simultaneously with conversion, or it can occur upstream
(in RS) or downstream (in IRS) of the conversion. Operations connected
with that re-ordering process shall hereafter be called "raster reading
(writing)" and "macro-block writing (reading)";
2) Conversion from macro-block format to block format, with interlaced
block scan (IBS) or progressive block scan (PBS) and vice versa.
Hereafter, for the sake of simplicity, the terms "interlaced block" or
"progressive block" shall be used. The two yes of block are possible only
for luminance and for a "frame" macro-block; in case of field macro-block,
only conversion to progressive block is possible. Conversion to
progressive block requires reading in sequence the first 8 pixels of all
rows of the macro-blocks, whereas in case of interlaced block, 8 pixels of
alternating rows will be read, since, as is well known, subsequent rows in
the macro-block pertain to different fields. For chrominance, reading
involves first the Cb pixel block and then the Cr pixel block;
3) Extraction of a prediction macro-block from a reference picture (or from
two reference pictures, in case of bi-directional compensation), i.e.
application of the motion vectors to the pixels of a macro-block stored in
the external memory to obtain a predicted macro-block. This function can
be performed along with an interpolation with half-pixel resolution. For
the sake of brevity, that function shall be called "macro-block
extraction": note that macro-block reading can be seen as an extraction in
which null vectors are applied, but the term "extraction" shall hereafter
be used only for the case of non-null motion vectors.
An additional function, similar to the previous one, is the extraction of a
so-called "zone" from a reference picture stored in the external memory.
The term "zone" indicates a set of data with pre-defined size, larger than
the macro-block size. This function can be used to process and refine the
prediction macro-block, before it is used. The size of the zone depend on
the video signal type (progressive or interlaced) and it may be, for
example, 22.times.18 (i.e. 18 rows of 22 pixels each) or 28.times.14 for
luminance, and 22.times.9 or 28.times.7 for chrominance. In case of zone
extraction, pixels of two different zones will actually be extracted.
FIG. 3 depicts the inputs and outputs of the circuit according to the
invention, indicated as MSM. The circuit, as previously stated, can be
associated with an external memory SD which, advantageously, comprises
SDRAM (Synchronous Dynamic RAM) elements. In the preferred embodiment of
the invention, MSM can co-operate with up to 4 elements, indicated in the
Figure as SD1 . . . SD4. By way of example, it is assumed that the
elements can store three pictures each. If SD comprises multiple elements,
these are written and read by MSM one at a time. Line 5 is a schematic
representation of the set of connections between MSM and SD for data
exchange and command transmission.
The way in which memory SD is organized holds no particular interest for
the purposes of the present invention. To make the description clearer,
where necessary reference shall be made to an example in which data in SD
are arranged by macro-blocks and a row is assigned to each macro-block.
Depending on the function circuit MSM has to perform, two writing modes
(raster and macro-block) and four reading modes (raster, macro-block
reading and extraction, zone extraction) will be possible. FIGS. 4A . . .
4D depict a picture portion subjected respectively to raster
writing/reading, macro-block writing/reading, macro-block extraction, zone
extraction. It should be stressed that the portion involved (bounded by
the thicker lines in FIGS. 4B-4D) is in any case read sequentially row by
row. In case of macro-block and zone extraction (FIGS. 4C, 4D) where the
picture portion to be read extends over different stored macro-blocks, the
term "quadrant" shall be used for the set of pixels to be extracted from
each of these macro-blocks.
Going back to FIG. 3, the inputs to MSM comprise:
a connection or bus 6 (picture bus) which carries the actual data to be
written into the external memory or to be transferred to the output after
macro-block/block format conversion or vice versa; bus 6 is advantageously
a 10-bit bus, since as previously stated the device can be used
immediately upstream or downstream of the transform (anti-transform)
computation circuits which require 10 significant bits;
a connection or bus 7 which carries the data synchronism signals;
a connection or bus 8 (information bus) which carries the parameters
required for processing incoming and outgoing samples when device MSM
operates in macro-block mode; the parameters of interest shall be examined
in the detailed description of the structure of device MSM; and
a connection or bus 9 for synchronism signals concerning parameter
extraction from bus 8.
The organization of the information on bus 8 and of the related synchronism
signals on bus 9 is described in patent application PCT/GB 95 01433.
MSM outputs are: two connections 10, 11 for data (8-bit connections) and a
connection 12 for synchronism signals. The two connections for the
outgoing data are necessary in the case of zone extraction, to allow
emission of all data in the available time, and in the case of 10-bit
output: in that case one of the connections carries the eight least
significant bits and the other one the two most significant bits.
With regard to synchronism, by way of non-limiting example reference will
be made to a clock frequency of 18 MHz on the picture bus and on the
information bus, and to a frequency of 36 MHz for reading/writing in SD.
The main synchronism signals of interest for an understanding of the
invention are: the picture synchronism signal (whose period is equal to
the duration of the 36.times.45 or 30.times.45 macro-blocks) and the
macro-block synchronism signal (whose period is equal to 420 pulses of the
18 MHz clock signal) when the circuit operates in macro-block mode; the
frame synchronism and line synchronism signals when input or output
signals are in raster format. Valid data signals are also provided.
It should be stressed that, in the macro-block time, the data of a
macro-block are to be written in SD, whereas data of two macro-blocks must
be read in certain operating modes. To allow this, the macro-block period
is divided into three parts. The first part, whose duration is about 100
pulses of the 18 MHz clock signal, is destined for writing, while the
other two parts, identical to each for other, are destined each to reading
a macro-block. That partition of the macro-block time is shown in FIG. 7B,
where the writing and reading intervals are denoted WR and RD,
respectively. The longer time interval assigned to reading a macro-block
stems from the greater complexity of reading operations, as it will be
better explained hereinafter.
FIG. 5 shows that in circuit MSM connections 6, 7 lead to a first internal
buffer memory, schematically represented with its control units by block
MT1. Outputs from MT1 comprise a connection 5a (belonging to line 5 shown
in FIG. 3), which carries data and some control signals, to be seen
further on, to external memory SD, and a pair of connections 50, 51 which,
when the device operates without using the external memory, supplies an
output interface SU with the data and synchronism signals to be
transferred on connections 10-12.
Connections 8 and 9, on the other hand, lead to a decoder DIB which, at the
appropriate instants, extracts parameters of interest for the specific
application from the stream present on the information bus and feeds them
to MT1 and/or to units ISS, CM. The latter units, in certain applications
of the device and in co-operation with a controller CME of the external
memory, provide for external memory addressing during writing (ISS) or
reading (CM) and for motion compensation (CM).
Data read from the external memory are received by device MSM through a bus
5b (which also belongs to line 5 shown in FIG. 3) which leads to an
interpolation unit IHV. That unit sends the data to a second internal
buffer memory, schematically represented with its control units by block
MT2, and then to output interface SU.
Circuit MSM also comprises a conventional microprocessor interface IU,
which allows connection with an external controller, not shown, which
provides for controlling, supervising and setting up the functions to be
performed. Control of communication between circuit MSM and the external
controller occurs by means of signals present on a connection 14.
Interface IU is also associated with a configuration register RC, which is
written by the external controller through a connection 13 and provides
all remaining units of the device, through bus 15, with information
concerning the function to be performed.
Instead of receiving the parameters of interest from information bus 8,
device MSM could receive such parameters from the external controller,
through connection 13 which also leads to unit DIB, to allow that kind of
operation. In any case, it is the task of the external controller to
provide the parameters required for information reception/emission in
raster format. The loading of the parameters provided by the external
controller into DIB is controlled by IU, through connection 30.
The device according to the invention could also be an autonomous device,
which does not employ an external controller. In that case connection 14
is wired so that signals present on it have a pre-set configuration, not
used for the signals generated by the controller. Connection 13 also is
wired so that signals on it represent appropriate configuration
parameters. Interface IU, when it recognizes the special configuration on
connection 14, will cause, through connection 31, information wired on
connection 13 to be loaded into RC.
For the sake of simplicity, FIG. 5 and the more detailed Figures which
follow do not show clock signals, reset signals and in general all those
signals which are not necessary for an understanding of the invention.
Note that the synchronization of operations performed by the various units
of the device is handled in a distributed fashion, by appropriate time
counters present in the units themselves.
The functions performed by the various units of MSM shall now be examined
in greater detail.
Buffer memory MT1 comprises two elements in ping-pong arrangement,
alternating in writing and reading operations at macro-block frequency.
The elements are structured in such a way as to store pixel pairs. During
the reading phase, blocks of 8 pixel pairs will be transferred to the
external memory or to the output. The structure of MT1 shall be described
in greater detail with reference to FIGS. 6A and 6B.
Unit DIB receives the parameters according to which data incoming to device
MSM (writing) and respectively data outgoing from the device (reading),
are to be processed, and extracts them according to the synchronism
signals present on connection 9. The parameters are organised in nibbles
(half-bytes) arranged in a pre-set order in the stream, so that their
meaning can immediately be deduced from the order in which they reach DIB.
Unit DIB therefore essentially comprises a nibble counter and two groups
of registers, to store the parameters for processing incoming and outgoing
data respectively. Each register group in turn comprises two sets of
registers which make available to downstream units the whole of the
information concerning the current picture and respectively the
information concerning the current macro-block.
In particular, in the writing phase, circuit DIB must extract, at picture
frequency, information about the type of encoded picture (I, P, B);
picture structure ("frame" or "field" and, in the tatter case, lower or
upper field); and the external memory element and position, inside the
element, where the picture is to be written.
Information at macro-block frequency of interest for writing is the type of
transform and, for macro-block/block conversion and vice versa, the block
format (progressive/interlaced).
For reading, the information required at picture frequency is the same as
for writing. At macro-block frequency, on the other hand, DIB extracts
motion compensation parameters, in particular:
compensation type (forward, backward, both or neither);
prediction mode: more specifically, for a "frame" type of picture,
prediction can be: "frame", concerning the complete macro-block and
requiring a single motion vector; "field", pertaining to the two fields
separately and requiring two motion vectors; "dual prime", consisting of a
double field prediction and of a crossed combination (lower-upper fields)
of the two predictions to yield the predicted macro-block, and requiring
four motion vectors. For the field picture, prediction can be: "field"
(wholly analogous to the "frame" prediction mentioned above); 16.times.8,
which concerns the upper or lower half of a macro-block and requires two
motion vectors; "dual prime", consisting of a double field prediction and
of a combination of the results and also requiring two motion vectors;
the vertical selection of the field, which indicates which field the motion
vector is to be applied to; and
motion vectors.
Unit ISS is a finite state machine which, when data need to be written in
macro-block format in SD, generates writing addresses for SD according to
the parameters provided by decoder DIB (wires 8a) and to signals MBC, MBS
which are provided by MT1 through connection 16 and represent the
co-ordinates of a column and of a stripe of macro-blocks in the picture.
Addresses are sent to CME through connection 18. Clearly, the address
generation law depends on the data arrangement in SD. Knowing that
arrangement, the person skilled in the art would have no problem in
designing logic network ISS.
Unit CM generates and sends to external memory controller CME address
signals and commands for reading in SD (FIG. 3) in one of the three
macro-block format reading modes (macro-block reading and extraction, zone
extraction). For that purpose CM receives reading parameters from DIB,
through wires 8b; moreover, through a connection 20, CM will exchange a
certain number of signals with CME and, through a connection 21, it
receives timing signals from MT2. Note that when data arrive at or have to
be emitted from MSM in raster format, circuit CM does not intervene and
CME is entirely tasked with addressing. The structure of CM is shown in
greater detail in FIG. 7.
Controller CME is tasked with driving the external memory addressing and
control signals, presented respectively on connections 5c, 5d, in the
different writing and reading modes described above. In case of raster
writing/reading, CME generates the addresses autonomously, whilst in the
other cases it receives the addresses from ISS, CM. The structure of CME
shall be described in greater detail with reference to FIG. 8.
Buffer memory MT2 comprises two pairs of elements in ping-pong arrangement,
alternating in writing and reading operations at macro-block frequency. A
pair of elements is needed to store data read from SD (FIG. 3), in place
of a single element as in MT1, as certain motion prediction and
compensation modes require a combination of pixels of picture pairs to be
performed and, in zone extraction, pixels from two zones are to be
emitted. Data to be written arrive in pairs from interpolator IHV and are
written sequentially (in frame or field mode). Writing and reading are
progressive, in frame or field mode. Reading is slaved, in terms of
timing, to reading from SD (FIG. 3). if both elements in a pair are to be
used, they are written one after the other and read concurrently.
Given these indications, designing MT2 does not present any problems to the
skilled worker in the art.
Pixels are transferred from unit MAT2 to output interface SU together with
valid data signals, present on a wire 52. SU performs any required pixel
combination or emits the data as they are read, if no combination is
required; moreover it associates the data with the synchronism and valid
data signals necessary in order the utilisation devices can recover the
data correctly. With regard to valid data signals, either the ones
provided by MT1 on a wire 51 or the ones provided by MT2 on a wire 52
shall be used, depending on the applications of device MSM. SU is
described in greater detail with reference to FIG. 9.
Unit IHV is to create a new macro-block whose pixels are the average
between adjacent pixels in the macro-block read from SD (interpolation).
Information needed to perform that function is represented by signals
H.sub.-- NT, V.sub.-- INT which, when active, request interpolation along
the horizontal and the vertical axis, respectively, of the macro-block.
Those signals are provided through connection 22 by motion compensation
unit CM, depending on the content of the motion vector, whose resolution
is half pixel. Processed data are transferred to unit MT2 through a
connection 23. Unit IHV comprises a control state machine and an operating
unit. The first one operates on the basis of signals H.sub.-- INT,
V.sub.-- INT and of an additional signal FS.sub.-- BYTE, also generated by
CM, which indicates whether, for each pixel pair, the first pixel is to be
processed or discarded. The operating unit, instead, is tasked with
computing the required averages (hence performing additions and
divisions). Unit IHV is transparent to data if device MSM is used for
conversion into raster format; if circuit MSM is used for zone extraction,
unit IHV only discards the first pixel, if necessary.
In FIG. 6A, RAM1, RAM2 indicate the two elements of the first buffer memory
MT1. Such elements receive addressing and control signals for writing and
reading respectively from two finite state machines WM1, RM1, by means of
a multiplexer MX1. Through MX1, the memory element which is being written
receives from WM1 also the data arriving at MSM (FIG. 3) through bus 6,
and the element which is being read transfers the data read to RM1 which
forwards them on bus 5a or 50. WM1 sends to multiplexer MX1 addresses and
data (through connections 60, 61), signals WE1, WE2 enabling
writing/reading into/from either element, and signals ME1, ME2 timing the
loading of an address or a datum into the memory. The outputs of WM1 on
which these control signals are present are represented schematically in
the whole by connection 62. The sequence of emission of writing commands,
addresses and data is the sequence typical for any memory and therefore a
more detailed description is not required. RM1 instead generates reading
addresses, sent to MX1 through a connection 63.
Outputs 61-i, 62-i, 64-i (i=1,2) from | | |
